Abstract: Embodiments of methods, apparatuses, and systems for signal processing of multiple input signals to control peak amplitudes of a combined signal are disclosed. One method includes receiving a plurality of input signals, generating a combined signal, the combined signal comprising a plurality of sub-channels, wherein each sub-channel includes a representation of at least a portion of at least one of the plurality of input signals, and processing the representation of the least a portion of the at least one of the plurality of input signals of at least one of the sub-channels, to reduce a peak-to-average-power ratio (PAR) of the combined signal.

Abstract: An apparatus and method of controlling activation of electronic circuitry of data ports of a communication system is disclosed. One method includes a first data port detecting a lack of data for transmission to a second data port. At least one of the first data port and a second data port deactivate electronic circuitry of at least one of the first and second data ports upon detection of the lack of data. The first and second data ports maintain synchronization with each other while the electronic circuitry is deactivated by periodically exchanging synchronization test patterns. At least one of the first data port and the second data port transmit an alert to the other of the first and second data port when data for communication is detected. The other of the first data port and the second data port activate electronic circuitry upon receiving the alert. At least one of the first data port and the second data port transmit data.

Abstract: An apparatuses and methods of setting power back-off of a master transceiver and a slave transceiver is disclosed. One example of a method includes the master transceiver determining a master power back-off, and the slave transceiver determining a slave power back-off based on signals received from the master transceiver, and based on the master power back-off. One example of an apparatus includes a master transceiver and slave transceiver system. The slave transceiver is connected to the master transceiver through a cable. The master transceiver includes means for determining a master power back-off. The slave transceiver includes means for determining a slave power back-off based on signals received from the master transceiver, and based on the master power back-off.

Abstract: Embodiments of methods, apparatuses, and systems for signal processing of multiple input signals to control peak amplitudes of a combined signal are disclosed. One method includes receiving a plurality of input signals, generating a combined signal, the combined signal comprising a plurality of sub-channels, wherein each sub-channel includes a representation of at least a portion of at least one of the plurality of input signals, and processing the representation of the least a portion of the at least one of the plurality of input signals of at least one of the sub-channels, to reduce a peak-to-average-power ratio (PAR) of the combined signal.

Abstract: An apparatuses and methods of setting power back-off of a master transceiver and a slave transceiver is disclosed. One example of a method includes the master transceiver determining a master power back-off, and the slave transceiver determining a slave power back-off based on signals received from the master transceiver, and based on the master power back-off. One example of an apparatus includes a master transceiver and slave transceiver system. The slave transceiver is connected to the master transceiver through a cable. The master transceiver includes means for determining a master power back-off. The slave transceiver includes means for determining a slave power back-off based on signals received from the master transceiver, and based on the master power back-off.

Abstract: An apparatus and method of interfacing physical layer (PHY) control with media access control (MAC) is disclosed. One method includes signaling to the PHY control to operate in a low-power mode when the MAC is detected to be transmitting idle patterns. The MAC transitioning from transmitting the idle patterns to transmitting data can be detected. When the transition is detected, the PHY control is signaled to transition to a wake up mode. Data from the MAC is buffered while the PHY control is in the wake up mode. The buffered data is provided to the PHY control after the PHY control has completed the wake up mode.

Abstract: An apparatus and method of controlling activation of electronic circuitry of data ports of a communication system is disclosed. One method includes a first data port detecting a lack of data for transmission to a second data port. At least one of the first data port and a second data port deactivate electronic circuitry of at least one of the first and second data ports upon detection of the lack of data. The first and second data ports maintain synchronization with each other while the electronic circuitry is deactivated by periodically exchanging synchronization test patterns. At least one of the first data port and the second data port transmit an alert to the other of the first and second data port when data for communication is detected. The other of the first data port and the second data port activate electronic circuitry upon receiving the alert. At least one of the first data port and the second data port transmit data.

Abstract: An apparatuses and methods of setting power back-off of a master transceiver and a slave transceiver is disclosed. One example of a method includes the master transceiver determining a master power back-off, and the slave transceiver determining a slave power back-off based on signals received from the master transceiver, and based on the master power back-off. One example of an apparatus includes a master transceiver and slave transceiver system. The slave transceiver is connected to the master transceiver through a cable. The master transceiver includes means for determining a master power back-off. The slave transceiver includes means for determining a slave power back-off based on signals received from the master transceiver, and based on the master power back-off.

Abstract: An apparatus and method of controlling activation of electronic circuitry of data ports of a communication system is disclosed. One method includes a first data port detecting a lack of data for transmission to a second data port. At least one of the first data port and a second data port deactivate electronic circuitry of at least one of the first and second data ports upon detection of the lack of data. The first and second data ports maintain synchronization with each other while the electronic circuitry is deactivated by periodically exchanging synchronization test patterns. At least one of the first data port and the second data port transmit an alert to the other of the first and second data port when data for communication is detected. The other of the first data port and the second data port activate electronic circuitry upon receiving the alert. At least one of the first data port and the second data port transmit data.

Abstract: An apparatus and method of setting power back-off of a master transceiver and a slave transceiver is disclosed. The method includes the master transceiver determining a master power back-off, and the slave transceiver determining a slave power back-off based on signals received from the master transceiver, and based on the master power back-off.

Abstract: An apparatus and method of interfacing physical layer (PHY) control with media access control (MAC) is disclosed. One method includes signaling to the PHY control to operate in a low-power mode when the MAC is detected to be transmitting idle patterns. The MAC transitioning from transmitting the idle patterns to transmitting data can be detected. When the transition is detected, the PHY control is signaled to transition to a wake up mode. Data from the MAC is buffered while the PHY control is in the wake up mode. The buffered data is provided to the PHY control after the PHY control has completed the wake up mode.

Abstract: A method and apparatus for receiving one of a plurality of Ethernet transmission protocol signals is disclosed. Each transmission protocol signal includes a plurality of transmission signal streams. The method includes determining which of the transmission protocol signals is being received. An analog front-end processor is connected to one of a plurality of protocol digital processors based on the transmission protocol signal being received. A setting of at least one functional parameter of the analog front-end processor and/or the protocol digital processors is selected based on the transmission protocol signal being received. A sampling rate of the analog front-end processor and/or a processing rate of the protocol digital processors are selected based on the transmission protocol signal being received. The plurality of transmission signal streams of the transmission protocol signal being received by the analog front-end processor are ADC sampled based on a shared clock source.

Abstract: An apparatus and method of aiding synchronization between a master transceiver and a slave transceiver is disclosed. The method includes the master transceiver transmitting data signals that are received by the slave transceiver. The slave transceiver locks a slave clock to the data signals with a slave phase-locked loop. The slave transceiver transmits slave clock information to the master transceiver.

Abstract: An apparatus and method of controlling activation of electronic circuitry of data ports of a communication system is disclosed. One method includes a first data port detecting a lack of data for transmission to a second data port. At least one of the first data port and a second data port deactivate electronic circuitry of at least one of the first and second data ports upon detection of the lack of data. The first and second data ports maintain synchronization with each other while the electronic circuitry is deactivated by periodically exchanging synchronization test patterns. At least one of the first data port and the second data port transmit an alert to the other of the first and second data port when data for communication is detected. The other of the first data port and the second data port activate electronic circuitry upon receiving the alert. At least one of the first data port and the second data port transmit data.

Abstract: An apparatus and method of aiding synchronization between a master transceiver and a slave transceiver is disclosed. The method includes the master transceiver transmitting data signals that are received by the slave transceiver. The slave transceiver locks a slave clock to the data signals with a slave phase-locked loop. The slave transceiver transmits slave clock information to the master transceiver.

Abstract: A method and apparatus for receiving one of a plurality of Ethernet transmission protocol signals is disclosed. Each transmission protocol signal includes a plurality of transmission signal streams. The method includes determining which of the transmission protocol signals is being received. An analog front-end processor is connected to one of a plurality of protocol digital processors based on the transmission protocol signal being received. A setting of at least one functional parameter of the analog front-end processor and/or the protocol digital processors is selected based on the transmission protocol signal being received. A sampling rate of the analog front-end processor and/or a processing rate of the protocol digital processors are selected based on the transmission protocol signal being received. The plurality of transmission signal streams of the transmission protocol signal being received by the analog front-end processor are ADC sampled based on a shared clock source.

Abstract: An apparatus and method of setting power back-off of a master transceiver and a slave transceiver is disclosed. The method includes the master transceiver determining a master power back-off, and the slave transceiver determining a slave power back-off based on signals received from the master transceiver, and based on the master power back-off.

Abstract: An equalizer, consisting of a plurality of taps, each tap having a multiplier which is coupled to multiply a respective input sample by a respective coefficient, the taps being arranged in sequence so that the input sample to each of the taps, except to a first tap in the sequence, is delayed relative to a preceding tap in the sequence. The equalizer further includes an input selector, which is coupled to toggle the input sample to at least a selected tap among the plurality of taps, responsive to a state of the equalizer, so that the equalizer operates in a first state as a feed forward equalizer, and in a second state as a blind equalizer.

Abstract: A finite impulse response filter, including a plurality of taps arranged to receive and process a sequence of input data samples so as to generate a filter output. Each tap consists of a multiplier operating in one's complement arithmetic, the multiplier being coupled to multiply a respective input sample from the sequence by a respective equalization coefficient, and an adder, which sums an output from the multiplier. The taps are arranged in sequence so that the input sample to each of the taps, except to a first tap in the sequence, is delayed relative to a preceding tap in the sequence. The filter also includes an adjustment-accumulator coupled to receive the filter output and responsive thereto to generate an adjustment that is adapted to correct the filter output to a twos complement result, and an adjustment-adder which sums the adjustment and the filter output to generate a final output.

Abstract: Apparatus for recovering timing of data input to a receiver, the apparatus consisting of an interpolator which receives the input data and generates interpolated-data in response to an interpolation coefficient, and a feed-forward equalizer having at least three taps. Each tap consists of a multiplier which is coupled to multiply a respective input sample by a respective adaptive equalization coefficient. The taps are arranged in sequence so that the input sample to each of the taps, except to a first tap in the sequence, is delayed relative to a preceding tap in the sequence. The equalizer receives and equalizes the interpolated-data so as to generate equalized-data from the interpolated-data. The apparatus also includes a timing sensor which adjusts the interpolation coefficient responsive a third adaptive equalization coefficient comprised in the equalization coefficients.