Patents by Inventor Dinakaran Chiadambaram

Dinakaran Chiadambaram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for reconfigurable at-speed test clock generator
    Patent number: 8432181
    Abstract: A reconfigurable number of at-speed pulses and reconfigurable dead cycles between pulses is utilized to enhance test coverage of an Integrated Circuit. A reconfigurable number of programmable at-speed phase-locked loop clock pulses without a dead cycle is emitted through an integrated circuit. Further, a plurality of programmable at-speed phase-locked loop clock pulses is emitted through the Integrated Circuit such that a reconfigurable number of dead cycles is between the plurality of programmable at-speed phase locked loop clock pulses. In addition, data associated with the reconfigurable number of programmable at-speed phase-locked loop clock pulses is capture. Finally, data associated with the reconfigurable number of dead cycles is captured.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: April 30, 2013
    Assignee: Thomson Licensing
    Inventor: Dinakaran Chiadambaram
  • METHOD AND APPARATUS FOR RECONFIGURABLE AT-SPEED TEST CLOCK GENERATOR
    Publication number: 20110102010
    Abstract: A reconfigurable number of at-speed pulses and reconfigurable dead cycles between pulses is utilized to enhance test coverage of an Integrated Circuit. A reconfigurable number of programmable at-speed phase-locked loop clock pulses without a dead cycle is emitted through an integrated circuit. Further, a plurality of programmable at-speed phase-locked loop clock pulses is emitted through the Integrated Circuit such that a reconfigurable number of dead cycles is between the plurality of programmable at-speed phase locked loop clock pulses. In addition, data associated with the reconfigurable number of programmable at-speed phase-locked loop clock pulses is capture. Finally, data associated with the reconfigurable number of dead cycles is captured.
    Type: Application
    Filed: July 25, 2008
    Publication date: May 5, 2011
    Inventor: Dinakaran Chiadambaram