Patents by Inventor Dinesh Annayya

Dinesh Annayya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for a high-speed frame tagger
    Patent number: 8774194
    Abstract: A method is described including extracting protocol information from a received packet within a framer, comparing the protocol information in a first pass to predetermined values to produce a first result, and tagging the packet based on the set of results.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: July 8, 2014
    Assignee: Ruction Capital Limited Liability Company
    Inventors: Velamur Krishnamachari Vasudevan, Dinesh Annayya
  • Method and Apparatus for a High-Speed Frame Tagger
    Publication number: 20120287945
    Abstract: A method is described including extracting protocol information from a received packet within a framer, comparing the protocol information in a first pass to predetermined values to produce a first result, and tagging the packet based on the set of results.
    Type: Application
    Filed: February 23, 2012
    Publication date: November 15, 2012
    Applicant: RUCTION CAPITAL LIMITED LIABILITY COMPANY
    Inventors: Velamur Krishnamachari Vasudevan, Dinesh Annayya
  • Method and apparatus for a high-speed frame tagger
    Patent number: 8135029
    Abstract: A method is described including extracting protocol information from a received packet within a framer, comparing the protocol information in a first pass to predetermined values to produce a first result, and tagging the packet based on the set of results.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: March 13, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Velamur Krishnamachari Vasudevan, Dinesh Annayya
  • Method and apparatus for a high-speed frame tagger
    Patent number: 7420975
    Abstract: In one embodiment, the invention is an apparatus. The apparatus includes a network processor interface suitable for coupling to a network processor. The apparatus further includes a central processor interface suitable for coupling to a central processor. The apparatus also includes a protocol determination logic block to determine a protocol type of data in a packet and steer the packet to either the central processor interface or the network processor interface based on the protocol type of data.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: September 2, 2008
    Assignee: Cypress Semiconductor Corporation
    Inventors: Velamur Krishnamachari Vasudevan, Dinesh Annayya
  • Cyclical redundancy check using nullifiers
    Patent number: 7290196
    Abstract: An architecture and method for cyclical redundancy check (CRC) calculation and checking is disclosed. This architecture may include a CRC calculation function, a plurality of CRC nullification functions, and a multiplexer to select the output of one of the plurality of CRC nullification functions. The architecture may further comprise N-1 CRC nullification functions, where N is number bytes in the data bus.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: October 30, 2007
    Assignee: Cypress Semiconductor Corporation
    Inventors: Dinesh Annayya, Vatan Kumar Verma