Abstract: A storage controller including a first controller. The first controller includes a memory module, a test access port controller, the test access port controller configured to control a built in self-test operation on the memory module, and a register configured to store a first instruction. In response to the storage controller detecting a test access port interface being accessible to the storage controller, the test access port controller is configured to control the built in self-test operation on the memory module of the first controller by having either (i) a second instruction sent from the test access port controller to the first controller or (ii) the first instruction sent from the register to the first controller. The first controller is configured to perform the built in self-test operation on the memory module in response to having received the first instruction or having received the second instruction.

Abstract: A circuit for reading data from a buffer memory, which is Synchronous Dynamic Random access Memory (“SDRAM”), or Double Data Rate-Synchronous Dynamic Random Access Memory (“DDR”) comprises logic for managing programmable clock signal relationships such that data that is read from the DDR is centered within a DQS signal which is generated from the DDR and then appropriately delayed.

Abstract: A memory system includes Synchronous Dynamic Random Access Memory (SDRAM) A memory controller communicates with the memory, generates an SDRAM clock signal, that receives a bi-directional sampling clock signal (DQS) that is generated based on the SDRAM clock signal, and reads data from the memory based on the DQS.

Abstract: A system and method for dynamically writing to and reading from an internal register space of a chip using a TAP controller without interfering with the normal operation of the chip is provided. Data that is to be written is loaded into a data register in the TAP controller before being written in the internal register space and the write instructions are loaded into an instruction register of the TAP controller. The address of the internal register space from where data is to be read is also loaded to the data register. Data is read and/or written from the internal register space after the TAP controller gets access to the internal register space via arbitration.

Abstract: A built in self test (BIST) system for a storage controller comprises a processor, a test access port (TAP) controller that communicates with a TAP interface that is external to the storage controller, and a BIST controller that selectively performs a BIST based on information received from each of the processor and the TAP controller.

Abstract: A memory system comprises a memory that includes at least one of Synchronous Dynamic Random Access Memory (SDRAM) and Double Data Rate SDRAM (DDR). A memory controller communicates with the memory, generates an SDRAM clock signal, and receives a bi-directional sampling clock signal (DQS). When the memory includes the DDR, the memory generates the DQS. When the memory includes the SDRAM, the DQS is based on the SDRAM clock signal.

Abstract: Method and system for initiating a built in self test (“BIST”) operation for memory modules is provided. The method includes, determining if a test access port (“TAP”) controller instruction or an internal register control bit are to be used for initiating the BIST operation; sending the internal register control bit to a memory BIST controller for initiating the BIST operation; and setting a status bit in the internal register after the BIST operation is complete. The system includes a storage controller with an internal register for setting a control bit for initiating a BIST operation; a test access port (“TAP”) controller for sending an instruction to a memory BIST controller to initiate a BIST operation; and a multiplexer for selecting between the control bit and the instruction for initiating the BIST operation.

Abstract: A system and circuit for reading and writing data to a buffer memory, which is Synchronous Dynamic Random access Memory (“SDRAM”), or Double Data Rate-Synchronous Dynamic Random Access Memory (“DDR”) is provided. The circuit includes logic for managing programmable clock signal relationships such that data arrives at an optimum time for writing. Data that is to be written at DDR is moved from a first buffer clock to a DDR write clock signal and to a DQS signal that is based on a SDRAM clock signal. Also, plural tap-cells may be used to delay clock signals such that data and clock signals are aligned. An emulated DQS signal in a DDR capture scheme is used for reading from a SDRAM.

Abstract: Method and system for initiating a built in self test (“BIST”) operation for memory modules is provided. The method includes, determining if a test access port (“TAP”) controller instruction or an internal register control bit are to be used for initiating the BIST operation; sending the internal register control bit to a memory BIST controller for initiating the BIST operation; and setting a status bit in the internal register after the BIST operation is complete. The system includes a storage controller with an internal register for setting a control bit for initiating a BIST operation; a test access port (“TAP”) controller for sending an instruction to a memory BIST controller to initiate a BIST operation; and a multiplexer for selecting between the control bit and the instruction for initiating the BIST operation.

Abstract: A system and circuit for reading and writing data to a buffer memory, which is Synchronous Dynamic Random access Memory (“SDRAM”), or Double Data Rate-Synchronous Dynamic Random Access Memory (“DDR”) is provided. The circuit includes logic for managing programmable clock signal relationships such that data arrives at an optimum time for writing. Data that is to be written at DDR is moved from a first buffer clock to a DDR write clock signal and to a DQS signal that is based on a SDRAM clock signal. Also, plural tap-cells may be used to delay clock signals such that data and clock signals are aligned. An emulated DQS signal in a DDR capture scheme is used for reading from a SDRAM.