Abstract: This disclosure describes an apparatus and method for simulating circuit designs. An apparatus for simulating circuit designs includes a first simulation vector processor (SVP) and a second SVP communicatively coupled to the first SVP. The first SVP simulates a first portion of a circuit design under test. The second SVP simulates the first portion of the circuit design under test at least partially while the first SVP simulates the first portion of the circuit design and asynchronously with the first SVP and transmits data to the first SVP while simulating the first portion of the circuit design, wherein the first SVP uses the data while simulating the first portion of the circuit design.

Abstract: A processing system for validating a circuit design, the processing system includes a flow processor, and an evaluation system coupled with the flow processor. The flow processor generates instructions from the circuit design. The evaluation system includes instruction memory circuitry receives the instructions from the flow processor and generate control signals, and interconnect circuitry receives the control signals routes a plurality of values based on the control signals. Each of the plurality of values having one of four states. The evaluation further includes operation circuitry that receives the plurality of values and the control signals, performs one or more operations of the circuit design with the plurality of values based on the control signals, and outputs operation values based on performing the one or more operations, the operation values indicative of an error within the circuit design.