Abstract: An ESD protection device comprises a substrate of a first conductive type; a transistor formed in the substrate having an input terminal of the first conductive type, a control terminal of a second conductive type, and a ground terminal of the first conductive type; and a diode formed in the substrate having a first terminal of the first conductive type and a second terminal of the second conductive type, wherein the input terminal and the second terminal are coupled to an input, and the ground terminal and the first terminal are coupled to a ground.

Abstract: An electrostatic discharge protection circuit includes a metal-oxide semiconductor transistor having a first terminal connected to an input end, and a gate connected to a supply voltage; a first bipolar junction transistor having a first terminal connected to the input end, and a base connected to a second terminal of the metal-oxide semiconductor transistor; a second bipolar junction transistor having a first terminal connected to the input end, a second terminal connected to the supply voltage, and a base connected to the second terminal of the first bipolar junction transistor; a first resistive device having a first end connected to the second terminal of the metal-oxide semiconductor transistor, and a second end connected to the supply voltage; and a second resistive device having a first end connected to the second terminal of the first bipolar junction transistor, and a second end connected to the supply voltage.

Abstract: An ESD protection device comprises a substrate of a first conductive type; a transistor formed in the substrate having an input terminal of the first conductive type, a control terminal of a second conductive type, and a ground terminal of the first conductive type; and a diode formed in the substrate having a first terminal of the first conductive type and a second terminal of the second conductive type, wherein the input terminal and the second terminal are coupled to an input, and the ground terminal and the first terminal are coupled to a ground.

Abstract: Electrostatic discharge (ESD) protection device in high voltage and the relevant manufacturing method is disclosed. The mentioned ESD protection device is disposed to bridge a ground and an input connected with an inner circuit to be protected. In which, the ESD protection device for high voltage comprises at least one PNP transistor and at least one diode connected in parallel, and an ESD discharging path is formed thereby. The PNP transistor is formed with an adjacent heavily doped P-type semiconductor zone (P+), lightly doped N-type semiconductor zone (N?), and a P-type semiconductor substrate. The diode is formed with an adjacent lightly doped N-type semiconductor zone and a light doped P-type semiconductor zone.

Abstract: An electrostatic discharge protection (ESD) circuit includes an NPN Darlington circuit and an n-type metal oxide semiconductor (NMOS) transistor. The drain of NMOS transistor is connected to the input end of the NPN Darlington circuit. The source of NMOS transistor is connected to the control end of the NPN Darlington circuit. The gate of NMOS transistor is connected to the output end of the NPN Darlington circuit.

Abstract: Electrostatic discharge (ESD) protection device in high voltage and the relevant manufacturing method is disclosed. The mentioned ESD protection device is disposed to bridge a ground and an input connected with an inner circuit to be protected. In which, the ESD protection device for high voltage comprises at least one PNP transistor and at least one diode connected in parallel, and an ESD discharging path is formed thereby. The PNP transistor is formed with an adjacent heavily doped P-type semiconductor zone (P+), lightly doped N-type semiconductor zone (N?), and a P-type semiconductor substrate. The diode is formed with an adjacent lightly doped N-type semiconductor zone and a light doped P-type semiconductor zone.

Abstract: An electrostatic discharge protection circuit includes a metal-oxide semiconductor transistor having a first terminal connected to an input end, and a gate connected to a supply voltage; a first bipolar junction transistor having a first terminal connected to the input end, and a base connected to a second terminal of the metal-oxide semiconductor transistor; a second bipolar junction transistor having a first terminal connected to the input end, a second terminal connected to the supply voltage, and a base connected to the second terminal of the first bipolar junction transistor; a first resistive device having a first end connected to the second terminal of the metal-oxide semiconductor transistor, and a second end connected to the supply voltage; and a second resistive device having a first end connected to the second terminal of the first bipolar junction transistor, and a second end connected to the supply voltage.

Abstract: An electrostatic discharge protection (ESD) circuit includes an NPN Darlington circuit and an n-type metal oxide semiconductor (NMOS) transistor. The drain of NMOS transistor is connected to the input end of the NPN Darlington circuit. The source of NMOS transistor is connected to the control end of the NPN Darlington circuit. The gate of NMOS transistor is connected to the output end of the NPN Darlington circuit.

Abstract: A new method is provided for the creation of an aluminum bump on a surface of a semiconductor device. A patterned layer of aluminum overlying a substrate is created, the patterned layer of aluminum is the layer of aluminum over which a contact bump is to be created. A layer of passivation is deposited, a first layer of photoresist is deposited for the creation of an opening in the layer of passivation that partially exposed the surface of the patterned layer of aluminum. This patterned first layer of photoresist remains in place, a layer of aluminum is sputter deposited, a second layer of photoresist is deposited which is patterned and etched for the creation of the aluminum bump overlying the patterned layer of aluminum. The aluminum solder bump is created by etching the deposited layer of aluminum. After the solder bump has been created, the patterned first and the second layers of photoresist are removed in one processing step, leaving in place the solder bump.

Abstract: A method is disclosed for forming an aluminum bump on an integrated circuit (IC) chip without leaving any metal residue on the passivation layer of the chip. This is accomplished by planarizing the passivation layer with spin-on-glass (SOG) and then forming a PECVD oxide as a sacrificial layer over the SOG, and etching through these layers to form an opening over a metal pad underlying the passivation layer. Then, a layer of aluminum is deposited over the substrate, including the opening, to form an aluminum bump. Aluminum bump is next formed by etching through a patterned oxide which acts as a hard mask over the aluminum layer. The SOG is then removed leaving the passivation layer free of any aluminum residue.