Abstract: An integrated circuit (IC) chip for transparent and in-service or production repair of single to multiple memory cell defects in a word during the datapath transit of the word between core memory to the interface of the IC via capturing an accurate bit from a word during a write access to a known defective memory address, and by substituting in a non-defective bit into the word during a read access from a known defective memory address. The IC includes: address matching circuit (CAM), a random access memory (RAM) of substitute memory cells containing accurate associated bit data and bit location in word of defect, and data selection circuitry (MUXs) coupled together.

Abstract: A memory device with a background built-in self-repair module (BBISRM) includes a main memory, an arbiter, and a redundant memory to repair a target memory under test (TMUT). The memory device also includes a background built-in self-test module (BBISTM) to identify portions of memory needing background built-in self-repair (BBISR). The BBISRM or the BBISTM can operate simultaneously while the memory device is operational for performing external accesses during field operation. The BBISR can detect and correct a single data bit error in the data stored in the TMUT. The arbiter configured to receive a read or write access memory request including a memory address, to determine if the memory address of the read or write access memory request matches the memory address mapped to the selected portion of the redundant memory, and to read or write data from the selected portion of the redundant memory, respectively.

Abstract: A memory device with background built-in self-testing (BBIST) includes a plurality of memory blocks; a memory buffer to offload data from one of the plurality of memory blocks temporarily; and a memory block stress controller to control a stress test applied to the one of the memory blocks when the data is temporarily offloaded on the memory buffer. The stress test tests for errors in the one of the plurality of the memory blocks.

Abstract: A memory device with a background built-in self-repair module (BBISRM) includes a main memory, an arbiter, and a redundant memory to repair a target memory under test (TMUT). The memory device also includes a background built-in self-test module (BBISTM) to identify portions of memory needing background built-in self-repair (BBISR). The BBISRM or the BBISTM can operate simultaneously while the memory device is operational for performing external accesses during field operation. The BBISR can detect and correct a single data bit error in the data stored in the TMUT. The arbiter configured to receive a read or write access memory request including a memory address, to determine if the memory address of the read or write access memory request matches the memory address mapped to the selected portion of the redundant memory, and to read or write data from the selected portion of the redundant memory, respectively.

Abstract: A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes a pair of cross-coupled inverters (or a similar latching circuit) coupled between the first and second bit lines, as well as a first select transistor coupling the first bit line to a first global bit line, and a second select transistor coupling the second bit line to a second global bit line. The first and second select transistors are independently controlled, thereby enabling improved read and write access sequences to be implemented, whereby signal loss associated with bit line coupling is eliminated, ‘read bump’ conditions are eliminated, and late write conditions are eliminated.

Abstract: An integrated circuit (IC) chip for transparent and in-service or production repair of single to multiple memory cell defects in a word during the datapath transit of the word between core memory to the interface of the IC via capturing an accurate bit from a word during a write access to a known defective memory address, and by substituting in a non-defective bit into the word during a read access from a known defective memory address. The IC includes: address matching circuit (CAM), a random access memory (RAM) of substitute memory cells containing accurate associated bit data and bit location in word of defect, and data selection circuitry (MUXs) coupled together.

Abstract: A memory device with background built-in self-testing (BBIST) includes a plurality of memory blocks; a memory buffer to offload data from one of the plurality of memory blocks temporarily; and a memory block stress controller to control a stress test applied to the one of the memory blocks when the data is temporarily offloaded on the memory buffer. The stress test tests for errors in the one of the plurality of the memory blocks.

Abstract: A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes a pair of cross-coupled inverters (or a similar latching circuit) coupled between the first and second bit lines, as well as a first select transistor coupling the first bit line to a first global bit line, and a second select transistor coupling the second bit line to a second global bit line. The first and second select transistors are independently controlled, thereby enabling improved read and write access sequences to be implemented, whereby signal loss associated with bit line coupling is eliminated, ‘read bump’ conditions are eliminated, and late write conditions are eliminated.

Abstract: A memory block includes a memory circuit and a clock generation unit. The memory circuit may output read data in response to receiving a read command and being clocked by a first clock signal having a selectable delay dependent upon a propagation delay for the read data to be output by a memory core. The clock generation unit is configured to generate a second clock signal having a selectable delay based on a system clock signal. The read data provided by the memory block in response to the second clock signal such that the read data has a latency that approximately the same, or is relatively fixed, for different frequencies of the system clock signal.

Abstract: A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes a pair of cross-coupled inverters (or a similar latching circuit) coupled between the first and second bit lines, as well as a first select transistor coupling the first bit line to a first global bit line, and a second select transistor coupling the second bit line to a second global bit line. The first and second select transistors are independently controlled, thereby enabling improved read and write access sequences to be implemented, whereby signal loss associated with bit line coupling is eliminated, ‘read bump’ conditions are eliminated, and late write conditions are eliminated.

Abstract: A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes a pair of cross-coupled inverters (or a similar latching circuit) coupled between the first and second bit lines, as well as a first select transistor coupling the first bit line to a first global bit line, and a second select transistor coupling the second bit line to a second global bit line. The first and second select transistors are independently controlled, thereby enabling improved read and write access sequences to be implemented, whereby signal loss associated with bit line coupling is eliminated, ‘read bump’ conditions are eliminated, and late write conditions are eliminated.

Abstract: A memory block includes a memory circuit and a clock generation unit. The memory circuit may output read data in response to being clocked by a clock signal having a selectable delay that may be dependent upon a time taken for the read data to be output by a memory core after the read command is received at the memory block. The clock generation unit may cause the read data to be provided as an output of the memory block in response to being clocked by a selected data clock signal. The data clock signal may be selected from one of several clock edges generated by one of several clock edges of a system clock such that regardless of the frequency of the system clock, the read data is provided by the memory block a predetermined amount of time after the read command is received at the memory block.

Abstract: A memory block includes a memory circuit and a clock generation unit. The memory circuit may output read data in response to being clocked by a clock signal having a selectable delay that may be dependent upon a time taken for the read data to be output by a memory core after the read command is received at the memory block. The clock generation unit may cause the read data to be provided as an output of the memory block in response to being clocked by a selected data clock signal. The data clock signal may be selected from one of several clock edges generated by one of several clock edges of a system clock such that regardless of the frequency of the system clock, the read data is provided by the memory block a predetermined amount of time after the read command is received at the memory block.