Abstract: The present invention provides a digital vertical multi-valued logic device including a substrate defining a horizontal plane and a vertical direction normal to the horizontal plane, a substantially vertical conductive gate structure disposed above the substrate, source and drain regions, a channel region positioned between the source and drain region and adjacent to the gate structure, the channel region including at least a first and second tunnel barrier forming a quantum well structure. The quantum well acts to incorporate an artificial bandstructure into the present invention modifying device performance. By introducing quantum wells into the device structure, quantum-mechanically defined drain voltage levels are introduced in the MOS transistors at which no current flows, creating stable intermediate logic levels.

Abstract: The present invention provides an interconnect structure which offers good mechanical stability and reduced charge concentration along the metal-insulator boundary corresponding to lower capacitance. The interconnect structure is comprised of a conductive transmission line structure and a transmission line support structure. The support structure has a "railway trestle-like" construction that provides a braced framework to support the transmission line with a greatly reduced effective dielectric constant. The trestle-like construction of the support structure is comprised of a membrane-like structure and supporting base structure separated by column-like support members. Spaces between the column-like support members form air pockets. The surface of the supporting base structure defines a horizontal axis. The long axis of the column-like support members are typically positioned at a 90 degree angle to the horizontal axis, thus defining a vertical axis support.

Abstract: A two-level metal connector having only one via level accommodates motion due to thermal expansion and manufacturing tolerances by decoupling vertical and lateral freedom of motions. The lateral motion from thermal expansion is small but strong, whereas the vertical motion is much larger because the connection must accommodate manufacturing tolerances of the solder bumps over the area of the die. By separating the horizontal and vertical displacements through a laterally-free anchor and flexible bridge, the height of the anchor may be made quite shallow while maintaining a comparatively large vertical distance for a probe tip to travel. Since the substrate is merely for structural support, the two-level metal connector can be placed over any substrate including one that already has many layers of metal.

Abstract: A multiple chip module (MCM) is fabricated by connecting a series of semiconductor chips, in a flip-chip orientation, to a multi-chip substrate with resilient connection pads. The substrate is formed from silicon by placing a layer of SiO2 on the surface. At the locations requiring a resilient connection pad, the SiO2 layer is pierced with a series of closely spaced holes. A cavity is etched out of the silicon below the closely spaced holes. The SiO2 layer is now suspended over the cavity and forms a flexible membrane. A post is formed on top of the flexible membrane. A conductor formed on the substrate has one end supported by the post. One end of the conductor is, therefor, supported by the post and flexible membrane so that a solder bump placed thereon may be used for a demountable connection to a contact pad on a flip-chip.

Abstract: A vertical CMOS semiconductor device and a method of making the device. A polysilicon gate post rises normal to a surface of a substrate. An annular transistor encircles the gate post. The transistor consists of a channel layer sandwiched between a pair of source/drain layers. Each layer lies directly above the layer beneath, with the gate post projecting up through the layers. One or more additional transistors of the same or differing polarities may be stacked above the first transistor, the various transistors being suitably spaced apart from each other. Electrical connections with the gate post and the various source/drain layers may be configured to provide a complementary inverter or some other circuit as desired.

Abstract: A multi-chip, self-aligning, integrated circuit flip-chip assembly using flexible connection assemblies for its attachment is enclosed in an integrated circuit package. The connection assembly contains connection pillars which are attached to a die and a carrier wafer by means of flexible membranes covering cavities in the respective components. Each pillar consists of two opposing connection posts, of die and carrier wafer, joined by a solder bump. A post is formed by etching a ring into the dielectric around predefined metal islands provided by the process, which are interconnected by respective vias to form a conductive core. The conductive path established between first layer metal interconnects of mating components via the connection pillars furnishes the electrical interface between chip and carrier in the flip chip arrangement.

Abstract: A multi-chip integrated circuit package includes a high-precision self-aligning assembly including a wafer with alignment apertures, a die with alignment slots and pin blocks for mating with both the apertures and the slots. The apertures, slots and pin blocks can be formed with walls along the <111> crystallographic plane so as to be oblique with respect to the <100> crystallographic planes defining the major wafer and die surfaces. These walls are defined photo-lithographically and formed using a highly anisotropic EDP etch. Electrical interfacing between die and wafer is provided using mating gold bumps and pads. The gold pads are formed on flexible silicon dioxide membranes. The membranes are formed over cavities which can be formed just as the apertures are formed. A second wafer with a silicon dioxide layer is bonded to the wafer with the cavities. Etching away the silicon substrate of the second wafer leaves a silicon dioxide membrane over the cavities.

Abstract: Small scale integrated chips are fabricated from a semiconductor wafer and subsequently pretested and formed into large area arrays with self aligning and self locking characteristics due to the axial orientation of the semiconductor wafer and geometries employed for the chips based upon the wafer orientation, whereby the spacing of abutting chip edges in an array may be less than 7 .mu.m. The chips are fabricated from <110> axial wafer, e.g., silicon <110> axial wafer, wherein the chip boundaries are aligned with vertical {111} planes of the crystalline material so that each of the chips formed from the wafer may be defined within parallelogrammatic like geometries defined by these planes and their intersections. The term "parallelogrammatic like geometries" means all geometric shapes capable of being formed with various vertical {111} planes within the crystalline structure of the wafer.

Abstract: An electron device resembling a MOS capacitor with two opposed terminals, except that the central dielectric substance includes a centralsemiconductor layer connected to a third terminal. An information carrying signal traveling depthwise through the layers is controlled by the variation of the depletion layers that are formed depthwise opposite each other by the action of the top and bottom electrodes. This control action takes the form of modulation of displacement current in the central dielectric substance. Pulse edge biasing of the device can cause two opposed depletion layers to approach each other in the central semiconductor layer achieving punch-through. An inverter circuit, formed by a pair of these devices forms the basis for a logic family. A transmission line, an EAROM, and a single-cell static random access memory are integrated circuit applications of the device.