Abstract: The invention relates to an enzymatic-chemical method for obtaining polyhydroxyalkanoates (PHA), especially polyhydroxybutyrate (PHB), or the copolymers thereof, from biomass. The inventive method comprises chemically treating the biomass with a reducing agent that reduces the non-PHA cell components of the biomass. The chemical treatment is carried out before and/or after enzymatic cell disruption. The inventive method allows, unlike other cell disruption techniques, for obtaining polyhydroxyalkanoates from biomass with a relatively low PHA content (for example <60%) without drastically changing or deteriorating the polymer properties or polymer purity.

Abstract: An apparatus for setting the spacing of a free standing range relative to a floor includes a base component for contacting the floor, a threaded element, and a winding follower. The winding follower extends into the helical recess of the threaded element such that the winding follower travels progressively further along the helical recess of the threaded element. A blocking member engages the winding follower during travel of the winding follower along the helical recess of the threaded element to resist a disengagement movement.

Abstract: The present invention relates to a novel method for fabricating a storage capacitor designed as a trench or a stacked capacitor and is used in particular in a DRAM memory cell. The method includes steps of forming a lower, metallic capacitor electrode, a storage dielectric and an upper capacitor electrode. The lower, metallic capacitor electrode is formed in a self-aligned manner on a silicon base material in such a way that uncovered silicon regions are first produced at locations at which the lower capacitor electrode will be formed, and then metal silicide is selectively formed on the uncovered silicon regions.

Abstract: The present invention relates to a novel method for fabricating a storage capacitor designed as a trench or a stacked capacitor and is used in particular in a DRAM memory cell. The method includes steps of forming a lower, metallic capacitor electrode, a storage dielectric and an upper capacitor electrode. The lower, metallic capacitor electrode is formed in a self-aligned manner on a silicon base material in such a way that uncovered silicon regions are first produced at locations at which the lower capacitor electrode will be formed, and then metal silicide is selectively formed on the uncovered silicon regions.

Abstract: A trench capacitor for use in a DRAM memory cell contains a lower capacitor electrode, a storage dielectric, and an upper capacitor electrode, which are at least partially disposed in a trench. The lower capacitor electrode adjoins, in a lower trench region, a wall of the trench, while in the upper trench region there is a spacer layer that adjoins a wall of the trench and is made from an insulating material. The upper electrode contains at least three layers, a first layer disposed in the trench on the storage dielectric and containing doped polysilicon, a second layer disposed on the first layer and containing metal-silicide, and a third layer disposed on the second layer and containing doped polysilicon. The layers of the upper electrode in each case extending along the walls and the base of the trench up to at least the upper edge of the spacer layer.

Abstract: In order to fabricate a semiconductor memory, a trench capacitor is arranged in a first trench. Beside the first trench, a first longitudinal trench and, parallel on the other side of the first trench, a second longitudinal trench are arranged in the substrate. A first spacer word line is arranged in the first longitudinal trench and a second spacer word line is arranged in the second longitudinal trench. There are arranged in the first trench connecting webs between the first spacer word line and the second spacer word line which have a thickness which, in the direction of the first spacer word line, is less than half the width of the first trench in the direction of the first spacer word line.

Abstract: A gate layer stack formed with at least two layers is firstly patterned anisotropically and then thelower layer is etched. An isotropic, preferably selective etching step effects a lateral undercutting, i.e. removal of the lower layer as far as the predetermined channel length to form a dimensionally accurate T-gate transistor with a very short channel length.

Abstract: In order to fabricate a semiconductor memory, a trench capacitor is arranged in a first trench. Beside the first trench, a first longitudinal trench and, parallel on the other side of the first trench, a second longitudinal trench are arranged in the substrate. A first spacer word line is arranged in the first longitudinal trench and a second spacer word line is arranged in the second longitudinal trench. There are arranged in the first trench connecting webs between the first spacer word line and the second spacer word line which have a thickness which, in the direction of the first spacer word line, is less than half the width of the first trench in the direction of the first spacer word line.

Abstract: A method for producing a silicon-on-insulator layer structure on a silicon surface with any desired geometry can locally produce the silicon-on-insulator structure. The method includes formation of mesopores in the silicon surface region, oxidation of the mesopore surface to form silicon oxide and rib regions from silicon in single-crystal form; and execution of a selective epitaxy process that that silicon grows on the uncovered rib regions, selectively with respect to the silicon oxide regions. Rib regions remain in place between adjacent mesopores, this step being ended as soon as a predetermined minimum silicon wall thickness of the rib regions is reached, the uncovering of the rib regions, which are arranged at the end remote from the semiconductor substrate between adjacent mesopores. The method can be used to fabricate a vertical transistor and a memory cell having a select transistor of this type.

Abstract: A gate layer stack formed with at least two layers is firstly patterned anisotropically and then the lower layer is etched. An isotropic, preferably selective etching step effects a lateral undercutting, i.e. removal of the lower layer as far as the predetermined channel length. This allows a T-gate transistor with a very short channel length to be fabricated dimensionally accurately, in a simple manner and cost-effectively. Its electrical switching properties are better than those of other T-gate transistors formed by conventional methods.

Abstract: The present invention relates to a novel method for fabricating a storage capacitor designed as a trench or a stacked capacitor and is used in particular in a DRAM memory cell. The method includes steps of forming a lower, metallic capacitor electrode, a storage dielectric and an upper capacitor electrode. The lower, metallic capacitor electrode is formed in a self-aligned manner on a silicon base material in such a way that uncovered silicon regions are first produced at locations at which the lower capacitor electrode will be formed, and then metal silicide is selectively formed on the uncovered silicon regions.

Abstract: A rotary switch configuration for a household appliance includes a rotary knob seated in a cutout in an appliance panel and firmly connected to an actuating shaft so as to rotate with it but move axially, the actuating shaft transmitting the rotary movement of the rotary knob to a switching shaft of a switching unit mounted behind the appliance panel. Exact and wobble-free guidance of the rotary knob is achieved by the actuating shaft being rotatably mounted on the appliance panel by a bearing device.

Abstract: A trench capacitor for use in a DRAM memory cell contains a lower capacitor electrode, a storage dielectric, and an upper capacitor electrode, which are at least partially disposed in a trench. The lower capacitor electrode adjoins, in a lower trench region, a wall of the trench, while in the upper trench region there is a spacer layer that adjoins a wall of the trench and is made from an insulating material. The upper electrode contains at least two layers, of which at least one is metallic, with the proviso that the upper electrode does not contain two layers of which the lower layer is tungsten silicide and the upper layer is doped polysilicon. The layers of the upper electrode in each case extending along the walls and the base of the trench up to at least the upper edge of the spacer layer.

Abstract: A rotary switch configuration for a household appliance includes a rotary knob seated in a cutout in an appliance panel and firmly connected to an actuating shaft so as to rotate with it but move axially, the actuating shaft transmitting the rotary movement of the rotary knob to a switching shaft of a switching unit mounted behind the appliance panel. Exact and wobble-free guidance of the rotary knob is achieved by the actuating shaft being rotatably mounted on the appliance panel by a bearing device.

Abstract: The invention is an electrochemical method for producing trenches for trench capacitors in p-doped silicon with a very high diameter/depth aspect ratio for large scale integrated semiconductor memories. Trenches (macropores) having a diameter of less than about 100 nm and a depth of more than 10 &mgr;m can be produced on p-doped silicon having a very low resistivity at a high etching rate, and thus, trench capacitors can be fabricated in a cost-effective manner.

Abstract: The invention relates to an enzymatic-chemical method for obtaining polyhydroxyalkanoates (PHA), especially poly-hydroxybutyrate (PHB), or the copolymers thereof, from biomass. The inventive method comprises chemically treating the biomass with a reducing agent that reduces the non-PHA cell components of the biomass. The chemical treatment is carried out before and/or after enzymatic cell disruption. The inventive method allows, unlike other cell disruption techniques, for obtaining polyhydroxyalkanoates from biomass with a relatively low PHA content (for example<60%) without drastically changing or deteriorating the polymer properties or polymer purity.

Abstract: A memory-cell array includes a substrate forming parallel first and second trenches. A transistor's upper source/drain region adjoins two of the first and two of the second trenches, and lies above its lower source/drain region. A conductive structure in a first trench associated with the transistor adjoins the upper source/drain region at its first edge. An insulating structure in the associated first trench insulates the conductive structure from a second edge and from a bottom of the associated first trench. A word line, on which is a further insulating layer, is over the upper/source drain region and parallel to the associated first trench bulges into the second trenches. Insulating spaces adjoin the word line laterally. A contact on the conductive structure and in electrical communication with the upper source/drain region connects with a capacitor.

Abstract: Semiconductor devices having deep trenches with fill material therein having low resistivity are provided along with methods of fabricating such semiconductor devices.

Abstract: The capacitor is arranged on the surface of a substrate. A first capacitor electrode has a middle part and a side part, which point vertically upwards, are arranged beside each other and are connected with each other via an upper part located above said middle part and said side part. The middle part is longer than the side part and is connected with other components of the circuit configuration located below said middle part and said side part. The first capacitor electrode is provided with a capacitor dielectric. A second capacitor electrode borders the capacitor dielectric.

Abstract: A first capacitor electrode of the capacitor, which is arranged on a surface of a substrate (1), has a lower part (T) and a lateral part (S) arranged thereon. At least a first lateral area of the lateral part (S) is undulatory in such a way that it has bulges and indentations alternately which are formed along lines each running in a plane parallel to the surface of the substrate (1). The lateral part (T) can be produced by depositing conductive material in a depression (V) which is produced in a layer sequence whose layers are composed alternately of a first material and a second material and in which the first material is subjected to wet etching selectively with respect to the second material down to a first depth. The first capacitor electrode is provided with a capacitor dielectric (KD). A second capacitor electrode (P) adjoins the capacitor dielectric (KD).