Patents by Inventor Dirk Wolansky
Dirk Wolansky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10832953Abstract: Method for producing a semiconductor device by providing a silicon wafer having a plurality of equal height raised portions on a first surface thereof; depositing an etch stop layer on the first surface; planarizing a surface of the etch stop layer; permanently bonding a first carrier wafer on the etch stop layer surface; producing components on or in a second wafer surface in a FEOL process; etching a plurality of trenches into the wafer, each trench formed at the respective location of one of the raised portions; depositing side wall insulation layers on side walls of the trenches; forming through-silicon vias by filling the trenches with electrically conductive material; producing a conductor path stack in a BEOL process for contacting the active components on the second surface; temporarily bonding a second carrier wafer onto a surface of the conductor path stack; removing the first carrier wafer and exposing the vias.Type: GrantFiled: September 28, 2017Date of Patent: November 10, 2020Assignee: IHP GMBH—INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS/LEIBNIZ-INSTITUT FUR INNOVATIVE MIKROELEKTRONIKInventors: Matthias Wietstruck, Mehmet Kaynak, Philip Kulse, Marco Lisker, Steffen Marschmeyer, Dirk Wolansky
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Publication number: 20180286751Abstract: Method for producing a semiconductor device by providing a silicon wafer having a plurality of equal height raised portions on a first surface thereof; depositing an etch stop layer on the first surface; planarizing a surface of the etch stop layer; permanently bonding a first carrier wafer on the etch stop layer surface; producing components on or in a second wafer surface in a FEOL process; etching a plurality of trenches into the wafer, each trench formed at the respective location of one of the raised portions; depositing side wall insulation layers on side walls of the trenches; forming through-silicon vias by filling the trenches with electrically conductive material; producing a conductor path stack in a BEOL process for contacting the active components on the second surface; temporarily bonding a second carrier wafer onto a surface of the conductor path stack; removing the first carrier wafer and exposing the vias.Type: ApplicationFiled: September 28, 2017Publication date: October 4, 2018Inventors: Matthias Wietstruck, Mehmet Kaynak, Philip Kulse, Marco Lisker, Steffen Marschmeyer, Dirk Wolansky
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Patent number: 9638617Abstract: Micro-electromechanical device for measuring the viscosity of a fluid, comprises a measuring chamber with a micromechanical actuator, arranged as a cantilever above a metallically conductive counter electrode, elastically deformable towards the counter electrode, surrounded by the fluid to be measured and made of a metallically conductive material, a two-terminal RF voltage source that can be switched off, having a first output terminal connected to the actuator, and a second output terminal connected to the counter electrode, and which is designed to output an RF voltage signal that is suitable for deflecting the actuator out of its rest position, and a measuring device to detect a change in the frequency, amplitude or phase of the RF signal in order to determine a measurement value for the viscosity-dependent speed at which the actuator is deformed.Type: GrantFiled: June 19, 2013Date of Patent: May 2, 2017Assignee: IHP GMBH—INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS/LEIBNIZ-INSTITUT FUR INNOVATIVE MIKROELEKTRONIKInventors: Mario Birkholz, Jurgen Drews, Karl-Ernst Ehwald, Dieter Genschow, Ulrich Haak, Philip Kulse, Egbert Matthus, Katrin Schulz, Wolfgang Winkler, Dirk Wolansky, Marlen Frohlich
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Publication number: 20140000344Abstract: Micro-electromechanical device for measuring the viscosity of a fluid, comprises a measuring chamber with a micromechanical actuator, arranged as a cantilever above a metallically conductive counter electrode, elastically deformable towards the counter electrode, surrounded by the fluid to be measured and made of a metallically conductive material, a two-terminal RF voltage source that can be switched off, having a first output terminal connected to the actuator, and a second output terminal connected to the counter electrode, and which is designed to output an RF voltage signal that is suitable for deflecting the actuator out of its rest position, and a measuring device to detect a change in the frequency, amplitude or phase of the RF signal in order to determine a measurement value for the viscosity-dependent speed at which the actuator is deformed.Type: ApplicationFiled: June 19, 2013Publication date: January 2, 2014Inventors: Mario Birkholz, Jurgen Drews, Karl-Ernst Ehwald, Dieter Genschow, Ulrich Haak, Philip Kulse, Egbert Matthus, Katrin Schulz, Wolfgang Winkler, Dirk Wolansky, Marlen Frohlich
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Patent number: 7595534Abstract: The invention relates to layers in substrate wafers. The aim of the invention is to provide layers in substrate wafers with which the drawbacks of conventional assemblies are overcome in order to achieve, on the one hand, an adequate resistance to latch-up in highly scaled, digital CMOS circuits with comparatively low costs and, on the other hand, to ensure low substrate losses/couplings for analog high-frequency circuits and, in addition, to influence the component behavior in a non-destructive manner.Type: GrantFiled: December 6, 2001Date of Patent: September 29, 2009Assignee: IHP GmbH-Innovations for High Performance Microelectronics/Institut fur Innovative MikroelektronikInventors: Bernd Heinemann, Karl-Ernst Ehwald, Dieter Knoll, Bernd Tillack, Dirk Wolansky, Peter Schley
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Patent number: 7244667Abstract: System for producing diffusion-inhibiting epitaxial semiconductor layers, by means of which thin diffusion-inhibiting, epitaxial semiconductor layers can be produced on large semiconductor substrates at a high throughput. The surfaces of the semiconductor substrates to be coated are first cleaned, and the substrates are then heated in a low pressure batch reactor to a first temperature (prebake temperature). The surfaces to be coated are next subjected to a hydrogen prebake operation at a first reactor pressure. In the next step the semiconductor substrates are heated in a low pressure hot or warm wall batch reactor to a second temperature (deposition temperature) lower than the first temperature, and after a condition of thermodynamic equilibrium is reached the diffusion-inhibiting semiconductor layers are deposited on the surfaces to be coated in a chemical gaseous deposition process (CVD) at a second reactor pressure higher than, equal to or lower than the first reactor pressure.Type: GrantFiled: July 25, 2002Date of Patent: July 17, 2007Inventors: Bernd Tillack, Dirk Wolansky, Georg Ritter, Thomas Grabolla
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Publication number: 20040266142Abstract: System for producing diffusion-inhibiting epitaxial semiconductor layers, by means of which thin diffusion-inhibiting, epitaxial semiconductor layers can be produced on large semiconductor substrates at a high throughput. The surfaces of the semiconductor substrates to be coated are first cleaned, and the substrates are then heated in a low pressure batch reactor to a first temperature (prebake temperature). The surfaces to be coated are next subjected to a hydrogen prebake operation at a first reactor pressure. In the next step the semiconductor substrates are heated in a low pressure hot or warm wall batch reactor to a second temperature (deposition temperature) lower than the first temperature, and after a condition of thermodynamic equilibrium is reached the diffusion-inhibiting semiconductor layers are deposited on the surfaces to be coated in a chemical gaseous deposition process (CVD) at a second reactor pressure higher than, equal to or lower than the first reactor pressure.Type: ApplicationFiled: August 16, 2004Publication date: December 30, 2004Inventors: Bernd Tillack, Dirk Wolansky, Georg Ritter, Thomas Grabolla
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Publication number: 20040075118Abstract: The invention relates to layers in substrate wafers. The aim of the invention is to provide layers in substrate wafers with which the drawbacks of conventional assemblies are overcome in order to achieve, on the one hand, an adequate resistance to latch-up in highly scaled, digital CMOS circuits with comparatively low costs and, on the other hand, to ensure low substrate losses/couplings for analog high-frequency circuits and, in addition, to influence the component behavior in a non-destructive manner.Type: ApplicationFiled: November 17, 2003Publication date: April 22, 2004Inventors: Bernd Heinemann, Karl-Ernst Ehwald, Dieter Knoll, Bernd Tillack, Dirk Wolansky, Peter Schley
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Patent number: 6465318Abstract: This invention relates to a bi-polar transistor and a procedure for its manufacture. The task of the invention is to propose a bi-polar transistor and a procedure for its manufacture that eliminates the disadvantages of conventional arrangements for a simple polysilicon technology with differential epitaxy for the manufacture of the base, in order to further improve especially the high-speed properties of a bi-polar transistor, to produce highly conductive connections between the metal contacts and the active (inner) transistor region as well as a minimized passive transistor surface, and to simultaneously avoid any additional process complexity and increased contact resistance. This invention resolves the task in that, by creating suitable epitaxy process conditions, the polysilicon layer is deposited on the insulator zone with a greater thickness than the epitaxy layer in the active transistor zone.Type: GrantFiled: August 2, 2001Date of Patent: October 15, 2002Assignee: Institut fuer Halbleiterphysik Franfurt (Oder) GmbHInventors: Karl-Ernst Ehwald, Bernd Tillack, Bernd Heinemann, Dieter Knoll, Dirk Wolansky