Abstract: A processor including a logic unit configured to execute multiple instructions being one of a speculative instruction or an architectural instruction is provided. The processor also includes a split cache comprising multiple lines, each line including a data accessed by an instruction and copied into the split cache from a memory address, wherein a line is identified as a speculative line for the speculative instruction, and as an architectural line for the architectural instruction. The processor includes a cache manager configured to select a number of speculative lines allocated in the split cache. The cache manager prevents an architectural line from being replaced by a speculative line based on a number of speculative lines allotted in the split cache, and manages the number of speculative lines to be allocated in the split cache based on the number of speculative lines relative to a number of architectural lines.

Abstract: A processor including a logic unit configured to execute multiple instructions being one of a speculative instruction or an architectural instruction is provided. The processor also includes a split cache comprising multiple lines, each line including a data accessed by an instruction and copied into the split cache from a memory address, wherein a line is identified as a speculative line for the speculative instruction, and as an architectural line for the architectural instruction. The processor includes a cache manager configured to select a number of speculative lines allocated in the split cache. The cache manager prevents an architectural line from being replaced by a speculative line based on a number of speculative lines allotted in the split cache, and manages the number of speculative lines to be allocated in the split cache based on the number of speculative lines relative to a number of architectural lines.

Abstract: A device including a logic unit configured to execute multiple instructions, and a schedule buffer that lists the instructions to be executed by the logic unit is provided. The device includes a fetch engine to retrieve data from an external memory, a cache including lines to hold the data associated with one of the instructions, including a spec-bit. The device includes a management unit to set the spec-bit to a speculative state when the data is retrieved for an instruction that has not been committed for execution by the logic unit, and to reset the spec-bit from a speculative state to a trusted state for a valid instruction. The management unit prevents the data from remaining in the cache when the spec-bit is in a speculative state. A computer system including the above device and a method of using the device are also provided.