Patents by Inventor Diyanesh B.C. Vidyapoornachary
Diyanesh B.C. Vidyapoornachary has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10891056Abstract: Systems, methods, and computer-readable media are disclosed for virtualizing memory compute function resources to improve resource utilization and system performance are disclosed. A virtualized hypervisor may be provided that is configured to instantiate a respective memory function controller of each memory controller present in a system/device. The virtualized hypervisor may be further configured to maintain the memory function controllers and their corresponding memory compute functionality as shareable resources that can be allocated to system components upon request. The virtualized hypervisor may allocate a memory function controller and its corresponding memory compute functionality to a system component, and may further provide the system component with an exclusive grant of memory compute pages that can be utilized by the allocated memory function controller to execute a memory compute function to perform one or more operations (e.g., one or more computations) on behalf of the system component.Type: GrantFiled: April 30, 2019Date of Patent: January 12, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edgar Cordero, Anand Haridass, Arun Joseph, Diyanesh B. C. Vidyapoornachary
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Patent number: 10497409Abstract: A method and apparatus for implementing row hammer avoidance in a dynamic random access memory (DRAM) in a computer system. Hammer detection logic identifies a hit count of repeated activations at a specific row in the DRAM. Monitor and control logic receiving an output of the hammer detection logic compares the identified hit count with a programmable threshold value. Responsive to a specific count as determined by the programmable threshold value, the monitor and control logic captures the address where a selected row hammer avoidance action is provided.Type: GrantFiled: December 17, 2014Date of Patent: December 3, 2019Assignee: International Business Machines CorporationInventors: Charles A. Kilmer, Anil B. Lingambudi, Warren E. Maule, Diyanesh B. C. Vidyapoornachary
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Publication number: 20190258399Abstract: Systems, methods, and computer-readable media are disclosed for virtualizing memory compute function resources to improve resource utilization and system performance are disclosed. A virtualized hypervisor may be provided that is configured to instantiate a respective memory function controller of each memory controller present in a system/device. The virtualized hypervisor may be further configured to maintain the memory function controllers and their corresponding memory compute functionality as shareable resources that can be allocated to system components upon request. The virtualized hypervisor may allocate a memory function controller and its corresponding memory compute functionality to a system component, and may further provide the system component with an exclusive grant of memory compute pages that can be utilized by the allocated memory function controller to execute a memory compute function to perform one or more operations (e.g., one or more computations) on behalf of the system component.Type: ApplicationFiled: April 30, 2019Publication date: August 22, 2019Inventors: EDGAR CORDERO, ANAND HARIDASS, ARUN JOSEPH, DIYANESH B. C. VIDYAPOORNACHARY
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Patent number: 10346050Abstract: Systems, methods, and computer-readable media are disclosed for virtualizing memory compute function resources to improve resource utilization and system performance are disclosed. A virtualized hypervisor may be provided that is configured to instantiate a respective memory function controller of each memory controller present in a system/device. The virtualized hypervisor may be further configured to maintain the memory function controllers and their corresponding memory compute functionality as shareable resources that can be allocated to system components upon request. The virtualized hypervisor may allocate a memory function controller and its corresponding memory compute functionality to a system component, and may further provide the system component with an exclusive grant of memory compute pages that can be utilized by the allocated memory function controller to execute a memory compute function to perform one or more operations (e.g., one or more computations) on behalf of the system component.Type: GrantFiled: October 26, 2016Date of Patent: July 9, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edgar R. Cordero, Ananda Haridass, Arun Joseph, Diyanesh B. C. Vidyapoornachary
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Patent number: 10209896Abstract: According to one aspect, a method for performance optimization of read functions in a memory system includes receiving, at the memory system, a read request including a logical address of a target data. The memory system includes a primary memory and a back-up memory that mirrors the primary memory. The method also includes searching a fault monitor table for an entry corresponding to the received logical address. The fault monitor table includes a plurality of entries that indicate physical locations of identified memory failure events in the primary memory and the back-up memory. Based on locating an entry corresponding to the received logical address, the method further includes selecting one of the primary memory and the backup memory for retrieving the target data. The selection is based on contents of the fault monitor table.Type: GrantFiled: October 12, 2016Date of Patent: February 19, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy J. Dell, Saravanan Sethuraman, Diyanesh B. C. Vidyapoornachary
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Publication number: 20180113612Abstract: Systems, methods, and computer-readable media are disclosed for virtualizing memory compute function resources to improve resource utilization and system performance are disclosed. A virtualized hypervisor may be provided that is configured to instantiate a respective memory function controller of each memory controller present in a system/device. The virtualized hypervisor may be further configured to maintain the memory function controllers and their corresponding memory compute functionality as shareable resources that can be allocated to system components upon request. The virtualized hypervisor may allocate a memory function controller and its corresponding memory compute functionality to a system component, and may further provide the system component with an exclusive grant of memory compute pages that can be utilized by the allocated memory function controller to execute a memory compute function to perform one or more operations (e.g., one or more computations) on behalf of the system component.Type: ApplicationFiled: October 26, 2016Publication date: April 26, 2018Inventors: Edgar R. Cordero, Anand Haridass, Arun Joseph, Diyanesh B. C. Vidyapoornachary
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Publication number: 20170031595Abstract: According to one aspect, a method for performance optimization of read functions in a memory system includes receiving, at the memory system, a read request including a logical address of a target data. The memory system includes a primary memory and a back-up memory that mirrors the primary memory. The method also includes searching a fault monitor table for an entry corresponding to the received logical address. The fault monitor table includes a plurality of entries that indicate physical locations of identified memory failure events in the primary memory and the back-up memory. Based on locating an entry corresponding to the received logical address, the method further includes selecting one of the primary memory and the backup memory for retrieving the target data. The selection is based on contents of the fault monitor table.Type: ApplicationFiled: October 12, 2016Publication date: February 2, 2017Inventors: Timothy J. Dell, Saravanan Sethuraman, Diyanesh B. C. Vidyapoornachary
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Publication number: 20170031787Abstract: According to one aspect, a method for performance optimization of read functions in a memory system includes receiving, at the memory system, a read request including a logical address of a target data. The memory system includes a primary memory and a back-up memory that mirrors the primary memory. The method also includes searching a fault monitor table for an entry corresponding to the received logical address. The fault monitor table includes a plurality of entries that indicate physical locations of identified memory failure events in the primary memory and the back-up memory. Based on locating an entry corresponding to the received logical address, the method further includes selecting one of the primary memory and the backup memory for retrieving the target data. The selection is based on contents of the fault monitor table.Type: ApplicationFiled: October 12, 2016Publication date: February 2, 2017Inventors: Timothy J. Dell, Saravanan Sethuraman, Diyanesh B. C. Vidyapoornachary
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Patent number: 9547449Abstract: According to one aspect, a method for performance optimization of read functions in a memory system includes receiving, at the memory system, a read request including a logical address of a target data. The memory system includes a primary memory and a back-up memory that mirrors the primary memory. The method also includes searching a fault monitor table for an entry corresponding to the received logical address. The fault monitor table includes a plurality of entries that indicate physical locations of identified memory failure events in the primary memory and the back-up memory. Based on locating an entry corresponding to the received logical address, the method further includes selecting one of the primary memory and the backup memory for retrieving the target data. The selection is based on contents of the fault monitor table.Type: GrantFiled: November 12, 2014Date of Patent: January 17, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy J. Dell, Saravanan Sethuraman, Diyanesh B. C. Vidyapoornachary
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Patent number: 9542110Abstract: According to one aspect, a method for performance optimization of read functions in a memory system includes receiving, at the memory system, a read request including a logical address of a target data. The memory system includes a primary memory and a back-up memory that mirrors the primary memory. The method also includes searching a fault monitor table for an entry corresponding to the received logical address. The fault monitor table includes a plurality of entries that indicate physical locations of identified memory failure events in the primary memory and the back-up memory. Based on locating an entry corresponding to the received logical address, the method further includes selecting one of the primary memory and the backup memory for retrieving the target data. The selection is based on contents of the fault monitor table.Type: GrantFiled: August 20, 2015Date of Patent: January 10, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy J. Dell, Saravanan Sethuraman, Diyanesh B.C. Vidyapoornachary
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Publication number: 20160180899Abstract: A method and apparatus for implementing row hammer avoidance in a dynamic random access memory (DRAM) in a computer system. Hammer detection logic identifies a hit count of repeated activations at a specific row in the DRAM. Monitor and control logic receiving an output of the hammer detection logic compares the identified hit count with a programmable threshold value. Responsive to a specific count as determined by the programmable threshold value, the monitor and control logic captures the address where a selected row hammer avoidance action is provided.Type: ApplicationFiled: December 17, 2014Publication date: June 23, 2016Inventors: Charles A. Kilmer, Anil B. Lingambudi, Warren E. Maule, Diyanesh B.C. Vidyapoornachary
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Publication number: 20160132259Abstract: According to one aspect, a method for performance optimization of read functions in a memory system includes receiving, at the memory system, a read request including a logical address of a target data. The memory system includes a primary memory and a back-up memory that minors the primary memory. The method also includes searching a fault monitor table for an entry corresponding to the received logical address. The fault monitor table includes a plurality of entries that indicate physical locations of identified memory failure events in the primary memory and the back-up memory. Based on locating an entry corresponding to the received logical address, the method further includes selecting one of the primary memory and the backup memory for retrieving the target data. The selection is based on contents of the fault monitor table.Type: ApplicationFiled: November 12, 2014Publication date: May 12, 2016Inventors: Timothy J. Dell, Saravanan Sethuraman, Diyanesh B.C. Vidyapoornachary
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Publication number: 20160132412Abstract: According to one aspect, a method for performance optimization of read functions in a memory system includes receiving, at the memory system, a read request including a logical address of a target data. The memory system includes a primary memory and a back-up memory that minors the primary memory. The method also includes searching a fault monitor table for an entry corresponding to the received logical address. The fault monitor table includes a plurality of entries that indicate physical locations of identified memory failure events in the primary memory and the back-up memory. Based on locating an entry corresponding to the received logical address, the method further includes selecting one of the primary memory and the backup memory for retrieving the target data. The selection is based on contents of the fault monitor table.Type: ApplicationFiled: August 20, 2015Publication date: May 12, 2016Inventors: Timothy J. Dell, Saravanan Sethuraman, Diyanesh B.C. Vidyapoornachary
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Patent number: 8984335Abstract: Embodiments of the disclosure are directed to an apparatus that comprises a first core susceptible to an error condition, and a second core configured to perform a diagnostic on the first core to identify a cause of the error condition and an action to remedy the error condition in order to recover the first core.Type: GrantFiled: March 15, 2013Date of Patent: March 17, 2015Assignee: International Business Machines CorporationInventors: Sreekala Anandavally, Anand Haridass, Gerard M. Salem, Diyanesh B. C. Vidyapoornachary
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Patent number: 8977895Abstract: Embodiments of the disclosure are directed to an apparatus that comprises a first core susceptible to an error condition, and a second core configured to perform a diagnostic on the first core to identify a cause of the error condition and an action to remedy the error condition in order to recover the first core.Type: GrantFiled: July 18, 2012Date of Patent: March 10, 2015Assignee: International Business Machines CorporationInventors: Sreekala Anandavally, Anand Haridass, Gerard M. Salem, Diyanesh B. C. Vidyapoornachary
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Publication number: 20140108859Abstract: Embodiments of the disclosure are directed to an apparatus that comprises a first core susceptible to an error condition, and a second core configured to perform a diagnostic on the first core to identify a cause of the error condition and an action to remedy the error condition in order to recover the first core.Type: ApplicationFiled: March 15, 2013Publication date: April 17, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sreekala Anandavally, Anand Haridass, Gerard M. Salem, Diyanesh B.C. Vidyapoornachary
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Publication number: 20140025991Abstract: Embodiments of the disclosure are directed to an apparatus that comprises a first core susceptible to an error condition, and a second core configured to perform a diagnostic on the first core to identify a cause of the error condition and an action to remedy the error condition in order to recover the first core.Type: ApplicationFiled: July 18, 2012Publication date: January 23, 2014Applicant: International Business Machines CorporationInventors: Sreekala Anandavally, Anand Haridass, Gerard M. Salem, Diyanesh B.C. Vidyapoornachary