Patents by Inventor Dmitri Pavlov

Dmitri Pavlov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Embedded branch prediction unit
    Patent number: 9753732
    Abstract: In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: September 5, 2017
    Assignee: Intel Corporation
    Inventors: Xiaowei Jiang, Srihari Makineni, Zhen Fang, Dmitri Pavlov, Ravi Iyer
  • Embedded Branch Prediction Unit
    Publication number: 20160283244
    Abstract: In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.
    Type: Application
    Filed: June 7, 2016
    Publication date: September 29, 2016
    Inventors: Xiaowei Jiang, Srihari Makineni, Zhen Fang, Dmitri Pavlov, Ravi Iyer
  • Embedded branch prediction unit
    Patent number: 9395994
    Abstract: In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: July 19, 2016
    Assignee: Intel Corporation
    Inventors: Xiaowei Jiang, Srihari Makineni, Zhen Fang, Dmitri Pavlov, Ravi Iyer
  • Using Reduced Instruction Set Cores
    Publication number: 20140258685
    Abstract: A processor may be built with cores that only execute some partial set of the instructions needed to be fully backwards compliant. Thus, in some embodiments power consumption may be reduced by providing partial cores that only execute certain instructions and not other instructions. The instructions not supported may be handled in other, more energy efficient ways, so that, the overall processor, including the partial core, may be fully backwards compliant.
    Type: Application
    Filed: December 30, 2011
    Publication date: September 11, 2014
    Inventors: Srihari Makineni, Steven R. King, Alexander Redkin, Joshua B. Fryman, Ravishankar Iyer, Pavel S. Smirnov, Dmitry Gusev, Dmitri Pavlov
  • Configurable Reduced Instruction Set Core
    Publication number: 20140223145
    Abstract: A processor may be built with cores that only execute some partial set of the instructions needed to be fully backwards compliant. Thus, in some embodiments power consumption may be reduced by providing partial cores that only execute certain instructions and not other instructions. The instructions not supported may be handled in other, more energy efficient ways, so that, the overall processor, including the partial core, may be fully backwards compliant.
    Type: Application
    Filed: December 30, 2011
    Publication date: August 7, 2014
    Applicant: Intel Corporation
    Inventors: Srihari Makineni, Steven R. King, Zhen Fang, Alexander Redkin, Ravishankar Iyer, Pavel S. Smirnov, Dmitry Gusev, Dmitri Pavlov, May Wu
  • Embedded Branch Prediction Unit
    Publication number: 20140019736
    Abstract: In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.
    Type: Application
    Filed: December 30, 2011
    Publication date: January 16, 2014
    Inventors: Xiaowei Jiang, Srihari Makineni, Zhen Fang, Dmitri Pavlov, Ravi Iyer