Patents by Inventor Dmitry E. Ryzhov

Dmitry E. Ryzhov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11729416
    Abstract: An embodiment of a semiconductor package apparatus may include technology to determine a residual error based on coding unit information, and determine a candidate coding unit and an associated rate distortion cost based on the residual error. An embodiment may additionally or alternatively include technology to partition a first coding unit into two or more smaller coding units based on a partition message, accelerate processing of at least one of the two or more smaller coding units, and estimate motion fora frame based at least partially on results of the accelerated processing. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 15, 2023
    Assignee: Intel Corporation
    Inventors: Srinivasan Embar Raghukrishnan, James M. Holland, Sang-Hee Lee, Atthar H. Mohammed, Dmitry E. Ryzhov, Jason Tanner, Lidong Xu, Wenhao Zhang
  • Publication number: 20230097092
    Abstract: Techniques related to video encoding include inline downscaling hardware in multi-pass encoding.
    Type: Application
    Filed: November 1, 2022
    Publication date: March 30, 2023
    Applicant: Intel Corporation
    Inventors: Shriram S. Deshpande, Satya N. Yedidi, James M. Holland, Dmitry E. Ryzhov, Jian Hu, Sai Agnihotri, Indira Munagani
  • Patent number: 11323700
    Abstract: Example apparatus to encode video disclosed herein include an encoder to perform an intra search first stage based on source pixels of a source video frame to determine first intra candidates to predict a block of the source video frame. In disclosed examples, the encoder is also to perform an intra search second stage based on reconstructed pixels of neighboring blocks associated with the first intra candidates to determine a second intra candidate. In disclosed examples, the encoder is further to encode the block of the source video frame based on the second intra candidate.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: James M. Holland, Srinivasan Embar Raghukrishnan, Zhijun Lei, Dmitry E. Ryzhov, Lidong Xu, Satya N. Yedidi
  • Patent number: 11025913
    Abstract: A system for video encoding is described herein. The system includes a processor to execute a multi-pass palette search and mapping on a video frame to generate palette candidates. The processor is to execute an intra block copy prediction on the video frame to generate intra-block-copy candidates. The processor is to also calculate a rate distortion optimization (RDO) cost for a set of generated residuals, the palette candidates, and the intra-block-copy candidates. The processor is to further also execute a final mode decision based on a comparison of the rate distortion optimization (RDO) costs.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: James M. Holland, Srinivasan Embar Raghukrishnan, Dmitry E. Ryzhov, Lidong Xu, Satya N. Yedidi, Wenhao Zhang
  • Publication number: 20210084294
    Abstract: Example apparatus to encode video disclosed herein include an encoder to perform an intra search first stage based on source pixels of a source video frame to determine first intra candidates to predict a block of the source video frame. In disclosed examples, the encoder is also to perform an intra search second stage based on reconstructed pixels of neighboring blocks associated with the first intra candidates to determine a second intra candidate. In disclosed examples, the encoder is further to encode the block of the source video frame based on the second intra candidate.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Inventors: James M. Holland, Srinivasan Embar Raghukrishnan, Zhijun Lei, Dmitry E. Ryzhov, Lidong Xu, Satya N. Yedidi
  • Patent number: 10855983
    Abstract: An example system includes a processor to execute an intra search first stage on a video frame to generate intra candidates. The processor is to execute an intra search second stage on the intra candidates to generate a final intra candidate and residuals. The processor is to also execute a final mode decision and generate reconstructed pixels based on the final intra candidate and the residuals.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: James M. Holland, Srinivasan Embar Raghukrishnan, Zhijun Lei, Dmitry E. Ryzhov, Lidong Xu, Satya N. Yedidi
  • Publication number: 20200314447
    Abstract: An embodiment of a semiconductor package apparatus may include technology to determine a residual error based on coding unit information, and determine a candidate coding unit and an associated rate distortion cost based on the residual error. An embodiment may additionally or alternatively include technology to partition a first coding unit into two or more smaller coding units based on a partition message, accelerate processing of at least one of the two or more smaller coding units, and estimate motion fora frame based at least partially on results of the accelerated processing. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: December 29, 2017
    Publication date: October 1, 2020
    Applicant: INTEL CORPORATION
    Inventors: Srinivas Embar Raghukrishnan, James M. Holland, Sang-Hee Lee, Atthar H. Mohammed, Dmitry E. Ryzhov, Jason Tanner, Lidong Xu, Wenhao Zhang
  • Patent number: 10555002
    Abstract: Techniques related to long term reference picture video coding are discussed. Such techniques include determining long term reference pictures for a sequence of pictures, adjusting the quantization parameters for the long term reference pictures based on temporal correlations for pictures temporally neighboring and including the long term reference pictures, and managing reference picture lists including the long term reference pictures.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Ximin Zhang, Sang-Hee Lee, Dmitry E. Ryzhov
  • Publication number: 20190297344
    Abstract: An example system includes a processor to execute an intra search first stage on a video frame to generate intra candidates. The processor is to execute an intra search second stage on the intra candidates to generate a final intra candidate and residuals. The processor is to also execute a final mode decision and generate reconstructed pixels based on the final intra candidate and the residuals.
    Type: Application
    Filed: June 13, 2019
    Publication date: September 26, 2019
    Applicant: INTEL CORPORATION
    Inventors: James M. Holland, Srinivasan Embar Raghukrishnan, Zhijun Lei, Dmitry E. Ryzhov, Lidong Xu, Satya N. Yedidi
  • Publication number: 20190261001
    Abstract: A system for video encoding is described herein. The system includes a processor to execute a multi-pass palette search and mapping on a video frame to generate palette candidates. The processor is to execute an intra block copy prediction on the video frame to generate intra-block-copy candidates. The processor is to also calculate a rate distortion optimization (RDO) cost for a set of generated residuals, the palette candidates, and the intra-block-copy candidates. The processor is to further also execute a final mode decision based on a comparison of the rate distortion optimization (RDO) costs.
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Applicant: INTEL CORPORATION
    Inventors: James M. Holland, Srinivasan Embar Raghukrishnan, Dmitry E. Ryzhov, Lidong Xu, Satya N. Yedidi, Wenhao Zhang
  • Patent number: 10291925
    Abstract: An apparatus of video encoding is described herein. The apparatus includes an encoder and a hardware bit packing unit. The encoder includes a fixed function hierarchical motion estimation search unit, fixed function integer motion estimation search units, and a fixed function check and refinement unit. The check and refinement unit is to generate residuals using nested loops based on at least one spatial domain prediction and at least one frequency domain prediction and perform a final mode decision based on rate distortion optimization (RDO) costs associated with the generated residuals. The hardware bit packing unit is to pack bits as coded according to the final mode decision into a data format.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: James M. Holland, Srinivasan Embar Raghukrishnan, Lidong Xu, Fangwen Fu, Dmitry E. Ryzhov, Satya N. Yedidi
  • Patent number: 10257529
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for dividing a frame comprising pixels into a number of macroblocks, each macroblock comprising a number of pixels within four macroblock boundaries. Various embodiments may also include creating at least two regions having a plurality of macroblocks by dividing the frame along macroblock boundaries and generating wave front groups based on the macroblocks in each region, each wave front group from each region comprising one or more macroblocks to process in parallel.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: April 9, 2019
    Assignee: INTEL CORPORATION
    Inventors: Changwon D. Rhee, Kin-Hang Cheung, Sang-Hee Lee, Zhijun Lei, Dmitry E. Ryzhov, Xinglei Zhu
  • Publication number: 20190037227
    Abstract: An apparatus of video encoding is described herein. The apparatus includes an encoder and a hardware bit packing unit. The encoder includes a fixed function hierarchical motion estimation search unit, fixed function integer motion estimation search units, and a fixed function check and refinement unit. The check and refinement unit is to generate residuals using nested loops based on at least one spatial domain prediction and at least one frequency domain prediction and perform a final mode decision based on rate distortion optimization (RDO) costs associated with the generated residuals. The hardware bit packing unit is to pack bits as coded according to the final mode decision into a data format.
    Type: Application
    Filed: July 28, 2017
    Publication date: January 31, 2019
    Applicant: Intel Corporation
    Inventors: James M. Holland, Srinivasan Embar Raghukrishnan, Lidong Xu, Fangwen Fu, Dmitry E. Ryzhov, Satya N. Yedidi
  • Patent number: 9872026
    Abstract: Techniques related to video coding with sample adaptive offset coding are discussed. Such techniques may include setting a sample adaptive offset coding flag for a picture of a group of pictures based at least in part on a comparison of an available coding bit limit of the picture to a first threshold and a quantization parameter of the picture to a second threshold. In some examples, such techniques may also include setting the sample adaptive offset coding flag based on a coding structure associated with coding the group of pictures.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: January 16, 2018
    Assignee: Intel Corporation
    Inventors: Ximin Zhang, Sang-Hee Lee, Dmitry E. Ryzhov
  • Publication number: 20170214938
    Abstract: Techniques related to long term reference picture video coding are discussed. Such techniques may include determining long term reference pictures for a sequence of pictures, adjusting the quantization parameters for the long term reference pictures, and managing reference picture lists.
    Type: Application
    Filed: January 21, 2016
    Publication date: July 27, 2017
    Inventors: Ximin Zhang, Sang-Hee Lee, Dmitry E. Ryzhov
  • Publication number: 20160366413
    Abstract: Techniques related to video coding with sample adaptive offset coding are discussed. Such techniques may include setting a sample adaptive offset coding flag for a picture of a group of pictures based at least in part on a comparison of an available coding bit limit of the picture to a first threshold and a quantization parameter of the picture to a second threshold. In some examples, such techniques may also include setting the sample adaptive offset coding flag based on a coding structure associated with coding the group of pictures.
    Type: Application
    Filed: June 12, 2015
    Publication date: December 15, 2016
    Inventors: Ximin Zhang, Sang-Hee Lee, Dmitry E. Ryzhov
  • Patent number: 9247256
    Abstract: Methods and systems may provide for utilizing a skip check module located in a video processing component to facilitate Scalable Video Coding (SVC) by determining cost relating to compression techniques. In one example, the method may include determining a location value associated with a current macro-block (MB), determining a source surface value associated with the current MB, determining a reference surface value associated with the current MB, determining a skip center value associated with the current MB, and calculating a cost value for utilizing a compression technique using the location value, the source surface value, the reference surface value, and the skip center value.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: January 26, 2016
    Assignee: Intel Corporation
    Inventors: Zhijun Lei, Dmitry E. Ryzhov
  • Publication number: 20150382021
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for divide a frame comprising pixels into a number of macroblocks, each macroblock comprising a number of pixels within four macroblock boundaries. Various embodiments may also include creating at least two regions having a plurality of macroblocks by dividing the frame along macroblock boundaries and generating wave front groups based on the macroblocks in each region, each wave front group from each region comprising one or more macroblocks to process in parallel.
    Type: Application
    Filed: June 30, 2014
    Publication date: December 31, 2015
    Inventors: Changwon D. Rhee, Kin-Hang Cheung, Sang-Hee Lee, Zhijun Lei, Dmitry E. Ryzhov, Xinglei Zhu
  • Publication number: 20140169470
    Abstract: Methods and systems may provide for utilizing a skip check module located in a video processing component to facilitate Scalable Video Coding (SVC) by determining cost relating to compression techniques. In one example, the method may include determining a location value associated with a current macro-block (MB), determining a source surface value associated with the current MB, determining a reference surface value associated with the current MB, determining a skip center value associated with the current MB, and calculating a cost value for utilizing a compression technique using the location value, the source surface value, the reference surface value, and the skip center value.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Inventors: Zhijun Lei, Dmitry E. Ryzhov