Patents by Inventor Do-Eung Kim

Do-Eung Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8248842
    Abstract: A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line of a plurality of first lines and a second terminal of the memory cell is connected to a corresponding second line of a plurality of second lines; a bias circuit for biasing a selected second line of the second lines to a reference voltage and a non-selected second line to a first voltage; and a local word line address decoder applying the reference voltage or a pumping voltage corresponding to the first voltage to the bias circuit.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: August 21, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Beak-Hyung Cho, Do-Eung Kim, Choong-Keun Kwak, Sang-Beom Kang, Woo-Yeong Cho, Hyung-Rok Oh
  • Publication number: 20100246248
    Abstract: A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line of a plurality of first lines and a second terminal of the memory cell is connected to a corresponding second line of a plurality of second lines; a bias circuit for biasing a selected second line of the second lines to a reference voltage and a non-selected second line to a first voltage; and a local word line address decoder applying the reference voltage or a pumping voltage corresponding to the first voltage to the bias circuit.
    Type: Application
    Filed: March 26, 2010
    Publication date: September 30, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: BEAK-HYUNG CHO, Do-Eung Kim, Choong-Keun Kwak, Sang-Beom Kang, Woo-Yeong Cho, Hyung-Rok Oh
  • Patent number: 7710767
    Abstract: A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: May 4, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Beak-Hyung Cho, Do-Eung Kim, Choong-Keun Kwak, Sang-Beom Kang, Woo-Yeong Cho, Hyung-Rok Oh
  • Publication number: 20080165575
    Abstract: A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.
    Type: Application
    Filed: January 4, 2008
    Publication date: July 10, 2008
    Inventors: Beak-Hyung Cho, Do-Eung Kim, Choong-Keun Kwak, Sang-Beom Kang, Woo-Yeong Cho, Hyung-Rok Oh