Abstract: A semiconductor device may be provided. The semiconductor device may be configured to shift storage positions of data and error information on the data to store the data into shifted storage positions based on the address signals having a certain combination being inputted a predetermined number of times.

Abstract: An error correction method includes performing a first error correction code (ECC) decoding operation of read data outputted from a memory medium and storing the read data outputted from the memory medium into a loop-buffer, in a first operation mode, and performing a second ECC decoding operation of the read data stored in the loop-buffer in a second operation mode.

Abstract: A semiconductor memory system including a resistive variable memory device and a driving method thereof are provided. The semiconductor memory system includes a memory controller including a scheduler configured to determine a generation period of a write command; a memory device including a memory cell array, the memory device being configured to write data input from the memory controller in the memory cell array in response to the write command; and a data determination circuit configured to output a change signal to the scheduler when all logic levels of the input data are equal to each other, the scheduler changing the generation period of the write command in response to the change signal.

Abstract: A semiconductor device may be provided. The semiconductor device may be configured to shift storage positions of data and error information on the data to store the data into shifted storage positions based on the address signals having a certain combination being inputted a predetermined number of times.

Abstract: An error correction method may include performing a first error correction code (ECC) decoding operation of read data outputted from a memory medium and storing the read data outputted from the memory medium into a loop-buffer, in a first operation mode, and performing a second ECC decoding operation of the read data stored in the loop-buffer may be performed in a second operation mode.

Abstract: A semiconductor device may be provided. The semiconductor device may be configured to shift storage positions of data and error information on the data to store the data into shifted storage positions based on the address signals having a certain combination being inputted a predetermined number of times.

Abstract: A memory system includes a memory medium, a loop-buffer configured to store read data outputted from the memory medium in a first operation mode, a fake-command generator configured to generate a fake-command in a second operation mode, and an error correction code (ECC) decoder configured to perform an ECC decoding operation of the read data stored in the loop-buffer in response to the fake-command.

Abstract: A read time-out manager may include a counter and a plurality of timers. The counter may generate a counter output signal based on a first cycle time. The plurality of timers may be each configured to be assigned a read identification to measure a time-out period corresponding to the read identification. Each of the plurality of timers may operate in synchronization with the counter output signal to generate a time-out signal based on a second cycle time different from the first cycle time.

Abstract: A semiconductor memory system includes a memory medium and a data input/output (I/O) pin repair control circuit. The memory medium includes a plurality of memory dies and a spare die. Each of the plurality of memory dies has a plurality of memory regions and a plurality of data I/O pins, and the spare die has a plurality of spare regions and a plurality of data I/O pins. The data I/O pin repair control circuit performs a repair process for replacing an abnormal data I/O pin among the plurality of data I/O pins included in any of the plurality of memory dies with a data I/O pin of the plurality of data I/O pins included in the spare die.

Abstract: A data transmission system includes a data transmitter and a data receiver. The data transmitter outputs ‘N’-bit transmission data (where ‘N’ denotes a natural number which is equal to or greater than two). The data receiver receives the ‘N’-bit transmission data through ‘N’-number of data transmission lines. The data receiver transmits a re-transmission request signal to the data transmitter when the ‘N’-bit transmission data inputted to the data receiver are erroneous data. The data transmitter divides the ‘N’-bit transmission data in response to the re-transmission request signal and operates in a first data re-transmission mode so that the divided transmission data are resent, together with first ground data, to the data receiver.

Abstract: A memory system includes: a memory device, including a plurality of memory cells, suitable for reading and writing data with a parity bit on a basis of a page; and a memory controller suitable for obtaining an error mask pattern based on compressed data when a number of error bits detected based on the data and the parity bit is equal to or less than a first threshold value and greater than a second threshold value, and controlling to write the compressed data, the parity bit updated based on the compressed data in which the error mask pattern is reflected, compression information on the compressed data and pattern information on the error mask pattern to the page.

Abstract: A semiconductor system may include: a volatile memory device that stores an address mapping table including mapping information for a non-volatile memory device; and a control device suitable for reading one or more seed values from the volatile memory device before the address mapping table is stored, generating a plurality of random values based on the seed values, and initializing mapping information to the plurality of random values.

Abstract: A memory system includes a memory medium, a loop-buffer configured to store read data outputted from the memory medium in a first operation mode, a fake-command generator configured to generate a fake-command in a second operation mode, and an error correction code (ECC) decoder configured to perform an ECC decoding operation of the read data stored in the loop-buffer in response to the fake-command.

Abstract: A memory system may include a memory device comprising a plurality of memory banks, and a memory controller suitable for allocating data of successive logical addresses to the respective memory banks, and controlling read/write operations of the data, wherein the memory controller groups pages of the respective memory banks, and performs a wear-leveling operation based on the read/write operations of the data on each group of the pages.

Abstract: A resistance variable memory apparatus may include a memory circuit configured to include a plurality of blocks, each including a plurality of memory cells. The resistance variable memory apparatus may include a disturbance preventing circuit configured to be driven based on a counting signal corresponding to the number of write accesses for each of the plurality of blocks, a write command, and an address signal and to allow scrubbing to be performed on a memory cell having a preset scrubbing condition when the counting signal satisfied with the scrubbing condition is output based on the scribing condition according to a physical position of the memory cell in the block.

Abstract: A data transmission system includes a data transmitter and a data receiver. The data transmitter outputs ‘N’-bit transmission data (where ‘N’ denotes a natural number which is equal to or greater than two). The data receiver receives the ‘N’-bit transmission data through ‘N’-number of data transmission lines. The data receiver transmits a re-transmission request signal to the data transmitter when the ‘N’-bit transmission data inputted to the data receiver are erroneous data. The data transmitter divides the ‘N’-bit transmission data in response to the re-transmission request signal and operates in a first data re-transmission mode so that the divided transmission data are resent, together with first ground data, to the data receiver.

Abstract: A memory controller may include an address control block. The address control block may be configured to remap a write target address when a number of write data having a first logic level is within a correctable range and when a level of a datum corresponding to the write target address has the first logic level.

Abstract: A semiconductor memory system including a resistive variable memory device and a driving method thereof are provided. The semiconductor memory system includes a memory controller including a scheduler configured to determine a generation period of a write command; a memory device including a memory cell array, the memory device being configured to write data input from the memory controller in the memory cell array in response to the write command; and a data determination circuit configured to output a change signal to the scheduler when all logic levels of the input data are equal to each other, the scheduler changing the generation period of the write command in response to the change signal.

Abstract: A memory system includes a memory medium and a memory controller. The memory medium includes data symbols and parity symbols which are respectively disposed at cross points of a plurality rows and a plurality of columns. The memory controller includes an error correction code (ECC) engine that is designed to execute an error correction operation at a fixed error correction level while the memory controller accesses the memory medium. The memory controller performs the error correction operation at the fixed error correction level using the ECC engine in a first error correction mode. The memory controller performs the error correction operation at an error correction level higher than the fixed error correction level using the ECC engine in a second error correction mode.

Abstract: A memory system may include: a memory device having a plurality of banks, each comprising a memory cell region including a plurality of memory cells, and a page buffer unit; and a controller suitable for receiving a write address and write data from a host, and controlling a write operation of the memory device, wherein the controller comprises: a page buffer table (PBT) comprising fields to retain the same data as the page buffer units of the respective banks; and a processor suitable for comparing the write data to data stored in a field of the PBT, corresponding to the write address, and controlling the memory device to write the write data or the data stored in the page buffer unit to memory cells selected according to the write address, based on a comparison result.