Abstract: In an overlay key used for measuring overlay accuracy between first and second layers on a substrate, a first mark may be formed in the first layer, and a second mark may be formed on the second layer. The first mark may include first patterns having a first pitch and extending in a first direction. The second mark may include second patterns extending in substantially the same direction as the first direction and having a second pitch substantially equal to the first pitch. First and second images may be acquired from the first and second marks. The overlay accuracy may be produced from position information of first and second interference fringes formed by overlaying a test image having a third pitch onto the first and second images.

Abstract: In an overlay key used for measuring overlay accuracy between first and second layers on a substrate, a first mark may be formed in the first layer, and a second mark may be formed on the second layer. The first mark may include first patterns having a first pitch and extending in a first direction. The second mark may include second patterns extending in substantially the same direction as the first direction and having a second pitch substantially equal to the first pitch. First and second images may be acquired from the first and second marks. The overlay accuracy may be produced from position information of first and second interference fringes formed by overlaying a test image having a third pitch onto the first and second images.

Abstract: Provided are a photomask and a method of fabricating a semiconductor device. The photomask includes a photomask substrate including a chip region and a scribe lane region, with an overlay mark formed in the scribe lane region. The overlay mark includes one or more sub-overlay marks. Each of the sub-overlay marks includes a plurality of unit regions sequentially connected to each other and having different widths, where the width of a given unit region is constant.

Abstract: Provided are a photomask and a method of fabricating a semiconductor device. The photomask includes a photomask substrate including a chip region and a scribe lane region, with an overlay mark formed in the scribe lane region. The overlay mark includes one or more sub-overlay marks. Each of the sub-overlay marks includes a plurality of unit regions sequentially connected to each other and having different widths, where the width of a given unit region is constant.

Abstract: An overlay mark includes at least one hole array formed on a semiconductor substrate and at least one linear trench adjacent to the hole array. The hole array may be formed adjacent to the linear trench along a predetermined direction. When alignment errors among patterns formed at predetermined portion of the semiconductor substrate are detected, the overlay mark may provide a contrast of light with a desired width and a high level so that alignment errors of patterns formed on the semiconductor substrate may be accurately detected and corrected using the overlay mark.

Abstract: An overlay key includes a main scale and a vernier scale, which traverse each other forming a plurality of crossings. The main scale includes a first main sub-scale and a second main sub-scale, which are separated from each other or at least partially overlap each other. The first and second main sub-scales extend in different directions such that they are not parallel to each other. The vernier scale includes a first vernier sub-scale and a second vernier sub-scale, which are separated from each other or at least partially overlap each other. The first and second vernier sub-scales extend in different directions such that they are not parallel to each other. Two measured crossings are obtained when the main scale and the vernier scale cross each other in a measured position. Then, overlay accuracy is measured from coordinate differences between reference crossings and the measured crossings.

Abstract: In an overlay key used for measuring overlay accuracy between first and second layers on a substrate, a first mark may be formed in the first layer, and a second mark may be formed on the second layer. The first mark may include first patterns having a first pitch and extending in a first direction. The second mark may include second patterns extending in substantially the same direction as the first direction and having a second pitch substantially equal to the first pitch. First and second images may be acquired from the first and second marks. The overlay accuracy may be produced from position information of first and second interference fringes formed by overlaying a test image having a third pitch onto the first and second images.

Abstract: An overlay key formed in a scribe lane and used to align a circuit pattern may include a lower overlay mark formed on a metal silicide layer directly in contact with a silicon substrate. A method of forming an overlay key in a scribe lane may include providing a silicon substrate, forming a metal silicide layer to be in direct contact with the silicon substrate, and forming a lower overlay mark on the metal silicide layer.

Abstract: A method of forming interconnection lines in a semiconductor device is disclosed. According to the method, a trench is formed in a semiconductor substrate and a scattered reflection layer is formed on the overall surface of the semiconductor substrate including the trench. The scattered reflection layer increases an optical energy reflection rate of a light source used in a photolithography process, thereby providing sufficient energy to completely expose photoresist used to form a photoresist pattern in the trench.

Abstract: An overlay mark includes at least one hole array formed on a semiconductor substrate and at least one linear trench adjacent to the hole array. The hole array may be formed adjacent to the linear trench along a predetermined direction. When alignment errors among patterns formed at predetermined portion of the semiconductor substrate are detected, the overlay mark may provide a contrast of light with a desired width and a high level so that alignment errors of patterns formed on the semiconductor substrate may be accurately detected and corrected using the overlay mark.

Abstract: A photoresist composition may include formulas 1 and 2: ?where R is an acetal group or a ter-butyloxy carbonyl (t-BOC) group, n and m are integers, n/(m+n) is 0.01?0.8, and m/(m+n) is 1?[n/(m+n)], ?where r is an integer between 8-40. A method for forming photoresist patterns may include forming a photoresist layer on a semiconductor substrate and exposing and developing the photoresist layer using a mask pattern that includes first areas having a light transmissivity of about 100% and second areas having a light transmissivity of between about 10% and about 30%.

Abstract: An overlay key includes a main scale and a vernier scale, which traverse each other forming a plurality of crossings. The main scale includes a first main sub-scale and a second main sub-scale, which are separated from each other or at least partially overlap each other. The first and second main sub-scales extend in different directions such that they are not parallel to each other. The vernier scale includes a first vernier sub-scale and a second vernier sub-scale, which are separated from each other or at least partially overlap each other. The first and second vernier sub-scales extend in different directions such that they are not parallel to each other. Two measured crossings are obtained when the main scale and the vernier scale cross each other in a measured position. Then, overlay accuracy is measured from coordinate differences between reference crossings and the measured crossings.

Abstract: A photoresist composition may include formulas 1 and 2: 1