Abstract: A method of operating an electronic converter is provided in which a switching activity of a switching stage of the electronic converter is active or inactive based on a control signal, and the method includes operating the electronic converter, alternatively, in a first or a second mode. In the first mode, the status signal is initially asserted and is de-asserted in response to an amplitude of the input sensing signal failing to reach a first reference threshold value. In the second mode, the status signal is initially de-asserted and an auxiliary power supply signal is periodically varied with a variation period. After a time interval equal to the variation period, a comparison signal is asserted in response to an amplitude of the sensed signal reaching a second reference threshold value. The status signal is asserted based on conditions of the comparison signal and the periodically varying auxiliary power supply signal.

Abstract: A method and apparatus for an active discharge of an X-capacitor are provided. A sensor signal, indicative of a voltage at the capacitor, is compared with a lower and upper threshold values. A first value of a smaller one of the lower and upper threshold values is increased to a first new value that is greater than a second value of a larger one of the lower and upper threshold values in response to a first control signal indicating the sensor signal is greater than the upper and lower threshold values. A third value of the greater one of the lower and upper threshold values is decreased to a second new value that is less than the value of the larger one of the lower and upper threshold values in response to a second control signal indicating the sensor signal is less than the upper and lower threshold values.

Abstract: A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.

Abstract: A system including an asynchronous finite state machine that transitions from a first state to a second state in response to receiving a virtual-clock event signal. The system further includes a trigger circuit that asserts a trigger signal when a first-state asynchronous event signal is asserted while the asynchronous finite state machine is in the first state. The system further including a virtual clock-pulse circuit configured to generate the virtual-clock event signal after receiving the trigger signal.

Abstract: A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.

Abstract: A method of operating an electronic converter is provided in which a switching activity of a switching stage of the electronic converter is active or inactive based on a control signal, and the method includes operating the electronic converter, alternatively, in a first or a second mode. In the first mode, the status signal is initially asserted and is de-asserted in response to an amplitude of the input sensing signal failing to reach a first reference threshold value. In the second mode, the status signal is initially de-asserted and an auxiliary power supply signal is periodically varied with a variation period. After a time interval equal to the variation period, a comparison signal is asserted in response to an amplitude of the sensed signal reaching a second reference threshold value. The status signal is asserted based on conditions of the comparison signal and the periodically varying auxiliary power supply signal.

Abstract: A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.

Abstract: A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.

Abstract: A time measurement includes a multiphase clock generator and a phase sampling circuit. The multiphase clock generator generates a sequence of a given number n of phase shifted clock phases, wherein one of the phase shifted clock phases represents a reference clock signal. The phase sampling circuit is configured to generate a phase value indicative of a number of fractions 1/n of the clock period of the clock phases elapsed between an edge of the reference clock signal and an instant when an asynchronous event signal is set. The phase sampling circuit includes first through fourth sub-circuits, which respectively generate or determine first through fourth control signals.

Abstract: A time measurement includes a multiphase clock generator and a phase sampling circuit. The multiphase clock generator generates a sequence of a given number n of phase shifted clock phases, wherein one of the phase shifted clock phases represents a reference clock signal. The phase sampling circuit is configured to generate a phase value indicative of a number of fractions 1/n of the clock period of the clock phases elapsed between an edge of the reference clock signal and an instant when an asynchronous event signal is set. The phase sampling circuit includes first through fourth sub-circuits, which respectively generate or determine first through fourth control signals.

Abstract: A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.

Abstract: An active discharge circuit discharges an X capacitor and includes a sensor circuit that generates a sensor signal indicative of an AC voltage at the X capacitor. A processing unit generates a reset signal as a function of a comparison signal. A comparator circuit generates the comparison signal by comparing the sensor signal with a threshold. A timer circuit sets a discharge enable signal to a first logic level when the timer circuit is reset via a reset signal. The timer circuit determines the time elapsed since the last reset and tests whether the time elapsed exceeds a given timeout value. If the time elapsed exceeds the given timeout value, the timer circuit sets the discharge enable signal to a second logic level. A dynamic threshold generator circuit varies the threshold of the comparator circuit as a function of the sensor signal.

Abstract: An active discharge circuit discharges an X capacitor and includes a sensor circuit that generates a sensor signal indicative of an AC voltage at the X capacitor. A processing unit generates a reset signal as a function of a comparison signal. A comparator circuit generates the comparison signal by comparing the sensor signal with a threshold. A timer circuit sets a discharge enable signal to a first logic level when the timer circuit is reset via a reset signal. The timer circuit determines the time elapsed since the last reset and tests whether the time elapsed exceeds a given timeout value. If the time elapsed exceeds the given timeout value, the timer circuit sets the discharge enable signal to a second logic level. A dynamic threshold generator circuit varies the threshold of the comparator circuit as a function of the sensor signal.

Abstract: An active discharge circuit discharges an X capacitor and includes a sensor circuit that generates a sensor signal indicative of an AC voltage at the X capacitor. A processing unit generates a reset signal as a function of a comparison signal. A comparator circuit generates the comparison signal by comparing the sensor signal with a threshold. A timer circuit sets a discharge enable signal to a first logic level when the timer circuit is reset via a reset signal. The timer circuit determines the time elapsed since the last reset and tests whether the time elapsed exceeds a given timeout value. If the time elapsed exceeds the given timeout value, the timer circuit sets the discharge enable signal to a second logic level. A dynamic threshold generator circuit varies the threshold of the comparator circuit as a function of the sensor signal.

Abstract: An active discharge circuit discharges an X capacitor and includes a sensor circuit that generates a sensor signal indicative of an AC voltage at the X capacitor. A processing unit generates a reset signal as a function of a comparison signal. A comparator circuit generates the comparison signal by comparing the sensor signal with a threshold. A timer circuit sets a discharge enable signal to a first logic level when the timer circuit is reset via a reset signal. The timer circuit determines the time elapsed since the last reset and tests whether the time elapsed exceeds a given timeout value. If the time elapsed exceeds the given timeout value, the timer circuit sets the discharge enable signal to a second logic level. A dynamic threshold generator circuit varies the threshold of the comparator circuit as a function of the sensor signal.

Abstract: A control device for a switching converter having a transformer, with a primary winding receiving an input quantity, a secondary winding providing an output quantity, an auxiliary winding providing a feedback quantity, and a switch element. The control device has a processing module for generating a control signal for switching the switch element on the basis of the feedback quantity in order to regulate the output quantity via alternation of phases of storage and transfer of energy. The processing module controls the end of the transfer phase by comparing the feedback quantity with a comparison threshold. A discrimination circuit generates a signal for discrimination between the presence of a short circuit on the output or the fact that the input quantity is lower than a threshold. The processing module controls the end of the energy-transfer phase also on the basis of the discrimination signal.

Abstract: A control device for a switching converter having a transformer, with a primary winding receiving an input quantity, a secondary winding providing an output quantity, an auxiliary winding providing a feedback quantity, and a switch element. The control device has a processing module for generating a control signal for switching the switch element on the basis of the feedback quantity in order to regulate the output quantity via alternation of phases of storage and transfer of energy. The processing module controls the end of the transfer phase by comparing the feedback quantity with a comparison threshold. A discrimination circuit generates a signal for discrimination between the presence of a short circuit on the output or the fact that the input quantity is lower than a threshold. The processing module controls the end of the energy-transfer phase also on the basis of the discrimination signal.

Abstract: An active discharge circuit discharges an X. The detection circuit includes a sensor circuit that generates a sensor signal indicative of an AC oscillation voltage at the X capacitor. The detection circuit also includes a processing unit that generates the reset signal as a function of a comparison signal. A comparator circuit generates the comparison signal by comparing the sensor signal with a threshold. A timer circuit sets a discharge enable signal to a first logic level when the timer circuit is reset via a reset signal. The timer circuit determines the time elapsed since the last reset and tests whether the time elapsed exceeds a given timeout value. If the time elapsed exceeds the given timeout value, the timer circuit sets the discharge enable signal to a second logic level. A dynamic threshold generator circuit varies the threshold of the comparator circuit as a function of the sensor signal.

Abstract: A peak detector circuit receives an oscillating power supply signal. A capacitor is selectably coupled to the signal and charged to a value corresponding to a peak value of the signal. A switch is then opened to isolate the capacitor. When the signal rises to within a selected threshold, relative to the stored value, a comparator produces a command signal to close the switch, again coupling the capacitor to the signal. The peak detector can also include a tracking circuit that controls the capacitor to track the oscillating signal while the switch is closed, a timer circuit that closes the switch and activates the tracking circuit if more than a selected time passes without production of a command signal, a circuit that controls the polarity of a leakage current of the capacitor, a further auxiliary capacitor and a further auxiliary switch with a further control logic.

Abstract: A peak detector circuit receives an oscillating power supply signal. A capacitor is selectably coupled to the signal and charged to a value corresponding to a peak value of the signal. A switch is then opened to isolate the capacitor. When the signal rises to within a selected threshold, relative to the stored value, a comparator produces a command signal to close the switch, again coupling the capacitor to the signal. The peak detector can also include a tracking circuit that controls the capacitor to track the oscillating signal while the switch is closed, a timer circuit that closes the switch and activates the tracking circuit if more than a selected time passes without production of a command signal, a circuit that controls the polarity of a leakage current of the capacitor, a further auxiliary capacitor and a further auxiliary switch with a further control logic.