Patents by Inventor Domingo A. Ferrer

Domingo A. Ferrer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11239336
    Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a niobium-based silicide layer. An IC structure according to the disclosure includes a transistor on a substrate, the transistor including a gate structure above the substrate and a source/drain (S/D) region on the substrate adjacent the gate structure. A niobium-based silicide layer is on at least an upper surface the S/D region of the transistor, and extends across substantially an entire width of the S/D region. An S/D contact to the S/D region is in contact with the niobium-based silicide layer.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: February 1, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Wei Hong, Yanping Shen, Domingo A. Ferrer, Hong Yu
  • Patent number: 11187852
    Abstract: Structures that include a Bragg grating and methods of fabricating a structure that includes a Bragg grating. The structure includes a waveguide core and a Bragg grating having a plurality of segments positioned with a spaced arrangement adjacent to the waveguide core. Each segment includes one or more exterior surfaces. The structure further includes a silicide layer located on the one or more exterior surfaces of each segment.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: November 30, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Yusheng Bian, Domingo Ferrer, Roderick A. Augur, Michal Rakowski
  • Publication number: 20210249518
    Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a niobium-based silicide layer. An IC structure according to the disclosure includes a transistor on a substrate, the transistor including a gate structure above the substrate and a source/drain (S/D) region on the substrate adjacent the gate structure. A niobium-based silicide layer is on at least an upper surface the S/D region of the transistor, and extends across substantially an entire width of the S/D region. An S/D contact to the S/D region is in contact with the niobium-based silicide layer.
    Type: Application
    Filed: February 12, 2020
    Publication date: August 12, 2021
    Inventors: Wei Hong, Yanping Shen, Domingo A. Ferrer, Hong Yu
  • Patent number: 10319633
    Abstract: A method of forming a titanium nitride (TiN) diffusion barrier includes exposing a deposition surface to a first pulse of a titanium-containing precursor and to a first pulse of a nitrogen-rich plasma to form a first TiN layer with a first nitrogen concentration making a lower portion of the TiN diffusion barrier, the first nitrogen concentration of the first TiN layer is increased by the first pulse of the nitrogen-rich plasma reducing a reactivity of the lower portion of the TiN diffusion barrier to prevent fluorine diffusion. The first TiN layer is exposed to second pulses of the titanium-containing precursor and the nitrogen-rich plasma to form a second TiN layer with a second nitrogen concentration above the first TiN layer making an upper portion of the TiN diffusion barrier, the first pulse of the nitrogen-rich plasma has a substantially longer duration than the second pulse of the nitrogen-rich plasma.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brett H. Engel, Domingo A. Ferrer, Arun Vijayakumar, Keith Kwong Hon Wong
  • Patent number: 10263065
    Abstract: Methods of forming a metal resistor are provided. The methods may include: depositing a metal layer, e.g., tungsten, on a substrate; and forming the metal resistor by implanting a semiconductor species, e.g., silicon and/or germanium, into the metal layer to form a semiconductor-metal alloy layer from at least a portion of the metal layer. In certain embodiments, an adhesion layer may be deposited by ALD prior to metal layer depositing. The metal resistor has a sheet resistance that remains substantially constant prior to and after subsequent annealing.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: April 16, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Domingo A. Ferrer Luppi, Aritra Dasgupta, Benjamin G. Moser
  • Patent number: 10192822
    Abstract: A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by implanting nitrogen into the structure.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Domingo A. Ferrer, Kriteshwar K. Kohli, Siddarth A. Krishnan, Joseph F. Shepard, Jr., Keith Kwong Hon Wong
  • Patent number: 10170359
    Abstract: A method of forming a titanium nitride (TiN) diffusion barrier includes exposing a deposition surface to a first pulse of a titanium-containing precursor and to a first pulse of a nitrogen-rich plasma to form a first TiN layer with a first nitrogen concentration making a lower portion of the TiN diffusion barrier, the first nitrogen concentration of the first TiN layer is increased by the first pulse of the nitrogen-rich plasma reducing a reactivity of the lower portion of the TiN diffusion barrier to prevent fluorine diffusion. The first TiN layer is exposed to second pulses of the titanium-containing precursor and the nitrogen-rich plasma to form a second TiN layer with a second nitrogen concentration above the first TiN layer making an upper portion of the TiN diffusion barrier, the first pulse of the nitrogen-rich plasma has a substantially longer duration than the second pulse of the nitrogen-rich plasma.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brett H. Engel, Domingo A. Ferrer, Arun Vijayakumar, Keith Kwong Hon Wong
  • Publication number: 20180374746
    Abstract: A method of forming a titanium nitride (TiN) diffusion barrier includes exposing a deposition surface to a first pulse of a titanium-containing precursor and to a first pulse of a nitrogen-rich plasma to form a first TiN layer with a first nitrogen concentration making a lower portion of the TiN diffusion barrier, the first nitrogen concentration of the first TiN layer is increased by the first pulse of the nitrogen-rich plasma reducing a reactivity of the lower portion of the TiN diffusion barrier to prevent fluorine diffusion. The first TiN layer is exposed to second pulses of the titanium-containing precursor and the nitrogen-rich plasma to form a second TiN layer with a second nitrogen concentration above the first TiN layer making an upper portion of the TiN diffusion barrier, the first pulse of the nitrogen-rich plasma has a substantially longer duration than the second pulse of the nitrogen-rich plasma.
    Type: Application
    Filed: August 31, 2018
    Publication date: December 27, 2018
    Inventors: Brett H. Engel, Domingo A. Ferrer, Arun Vijayakumar, Keith Kwong Hon Wong
  • Patent number: 10096609
    Abstract: A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by changing the crystalline structure to a tetragonal tungsten silicon layer.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: October 9, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Nicolas L. Breil, Domingo A. Ferrer, Keith Kwong Hon Wong
  • Publication number: 20180166402
    Abstract: A semiconductor device includes a metal thin film such as an eFUSE or a precision resistor above and laterally displaced from an interconnect structure. A first dielectric layer is disposed over the interconnect structure and optionally under the metal thin film, and is adapted to prevent etching of the interconnect structure during patterning of the metal thin film. Contacts to the metal thin film and the interconnect are made through a second dielectric layer that is disposed over the metal thin film and over the interconnect.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 14, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Viraj SARDESAI, William HENSON, Domingo FERRER LUPPI, Scott ALLEN, Emre ALPTEKIN
  • Publication number: 20180047622
    Abstract: A method of forming a titanium nitride (TiN) diffusion barrier includes exposing a deposition surface to a first pulse of a titanium-containing precursor and to a first pulse of a nitrogen-rich plasma to form a first TiN layer with a first nitrogen concentration making a lower portion of the TiN diffusion barrier, the first nitrogen concentration of the first TiN layer is increased by the first pulse of the nitrogen-rich plasma reducing a reactivity of the lower portion of the TiN diffusion barrier to prevent fluorine diffusion. The first TiN layer is exposed to second pulses of the titanium-containing precursor and the nitrogen-rich plasma to form a second TiN layer with a second nitrogen concentration above the first TiN layer making an upper portion of the TiN diffusion barrier, the first pulse of the nitrogen-rich plasma has a substantially longer duration than the second pulse of the nitrogen-rich plasma.
    Type: Application
    Filed: October 30, 2017
    Publication date: February 15, 2018
    Inventors: Brett H. Engel, Domingo A. Ferrer, Arun Vijayakumar, Keith Kwong Hon Wong
  • Publication number: 20180026118
    Abstract: During a physical vapor deposition (PVD) process, the ion energy of a depositing species is controlled. By varying the ion energy throughout the process, the degree of conformality of the deposited layer over three-dimensional structures, including the extent to which the deposited layer merges between adjacent structures can be controlled.
    Type: Application
    Filed: July 22, 2016
    Publication date: January 25, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Nicolas L. Breil, Neal A. Makela, Praneet Adusumilli, Domingo A. Ferrer
  • Patent number: 9859403
    Abstract: During a physical vapor deposition (PVD) process, the ion energy of a depositing species is controlled. By varying the ion energy throughout the process, the degree of conformality of the deposited layer over three-dimensional structures, including the extent to which the deposited layer merges between adjacent structures can be controlled.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: January 2, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Nicolas L. Breil, Neal A. Makela, Praneet Adusumilli, Domingo A. Ferrer
  • Patent number: 9847251
    Abstract: A method of forming a titanium nitride (TiN) diffusion barrier includes exposing a deposition surface to a first pulse of a titanium-containing precursor and to a first pulse of a nitrogen-rich plasma to form a first TiN layer with a first nitrogen concentration making a lower portion of the TiN diffusion barrier, the first nitrogen concentration of the first TiN layer is increased by the first pulse of the nitrogen-rich plasma reducing a reactivity of the lower portion of the TiN diffusion barrier to prevent fluorine diffusion. The first TiN layer is exposed to second pulses of the titanium-containing precursor and the nitrogen-rich plasma to form a second TiN layer with a second nitrogen concentration above the first TiN layer making an upper portion of the TiN diffusion barrier, the first pulse of the nitrogen-rich plasma has a substantially longer duration than the second pulse of the nitrogen-rich plasma.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: December 19, 2017
    Assignee: International Business Machines Corporation
    Inventors: Brett H. Engel, Domingo A. Ferrer, Arun Vijayakumar, Keith Kwong Hon Wong
  • Patent number: 9793216
    Abstract: Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method according to embodiments of the present disclosure can include: providing a structure including a via including a bulk semiconductor material therein, wherein the via further includes a cavity extending from a top surface of the via to an interior surface of the via, and wherein a portion of the bulk semiconductor material defines at least one sidewall of the cavity; forming a first metal level on the via, wherein the first metal level includes a contact opening positioned over the cavity of the via; forming a metal plug within the cavity to the surface of the via, such that the metal plug conformally contacts a sidewall of the cavity and the interior surface of the via, wherein the metal plug is laterally distal to an exterior sidewall of the via; and forming a contact within the contact opening of the first metal level.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: October 17, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Joyeeta Nag, Jim Shih-Chun Liang, Domingo A. Ferrer Luppi, Atsushi Ogino, Andrew H. Simon, Michael P. Chudzik
  • Publication number: 20170213792
    Abstract: Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method according to embodiments of the present disclosure can include: providing a structure including a via including a bulk semiconductor material therein, wherein the via further includes a cavity extending from a top surface of the via to an interior surface of the via, and wherein a portion of the bulk semiconductor material defines at least one sidewall of the cavity; forming a first metal level on the via, wherein the first metal level includes a contact opening positioned over the cavity of the via; forming a metal plug within the cavity to the surface of the via, such that the metal plug conformally contacts a sidewall of the cavity and the interior surface of the via, wherein the metal plug is laterally distal to an exterior sidewall of the via; and forming a contact within the contact opening of the first metal level.
    Type: Application
    Filed: January 26, 2016
    Publication date: July 27, 2017
    Inventors: Joyeeta Nag, Jim Shih-Chun Liang, Domingo A. Ferrer Luppi, Atsushi Ogino, Andrew H. Simon, Michael P. Chudzik
  • Patent number: 9691658
    Abstract: A method of forming an electrical contact in an integrated circuit, and an integrated circuit are disclosed. In an embodiment, the integrated circuit comprises a substrate, an insulating layer, and a metal layer. An opening is formed through the insulating layer to expose an active area of the substrate. The metal layer forms a cusp at a top end of the opening, narrowing this end of the opening. In embodiments, the method comprises depositing a conductive layer in the opening to form a liner, applying a filler material inside the opening to protect a portion of the liner, removing the cusp to widen the top of the opening while the filler material protects the portion of the liner covered by this material, removing the filler material from the opening, re-lining the opening, and filling the opening with a conductive material to form a contact through the insulating layer.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: June 27, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Emre Alptekin, Raghu Mangu, Cung D. Tran, Domingo A. Ferrer
  • Publication number: 20170125509
    Abstract: Methods of forming a metal resistor are provided. The methods may include: depositing a metal layer, e.g., tungsten, on a substrate; and forming the metal resistor by implanting a semiconductor species, e.g., silicon and/or germanium, into the metal layer to form a semiconductor-metal alloy layer from at least a portion of the metal layer. In certain embodiments, an adhesion layer may be deposited by ALD prior to metal layer depositing. The metal resistor has a sheet resistance that remains substantially constant prior to and after subsequent annealing.
    Type: Application
    Filed: November 4, 2015
    Publication date: May 4, 2017
    Inventors: Domingo A. Ferrer Luppi, Aritra Dasgupta, Benjamin G. Moser
  • Patent number: 9633946
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to seamless metallization structures and methods of manufacture. A structure includes: a contact opening formed in an oxide material and in alignment with an underlying structure; a metal liner lining the sidewalls and bottom of the contact opening, in direct electrical contact with the underlying structure; a conductive liner on the metal liner, within the contact opening; and tungsten fill material on the conductive liner and within the contact opening.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: April 25, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jim Shih-Chun Liang, Domingo A. Ferrer, Kathryn T. Schonenberg, Shahrukh Akbar Khan, Wei-Tsu Tseng
  • Patent number: 9583397
    Abstract: One aspect of the disclosure relates to a contact within a dielectric layer to a source/drain terminal of a field-effect-transistor (FET). The contact may include: a titanium-tantalum-silicide at a surface of the source/drain terminal; a barrier layer over the titanium-tantalum-silicide; and a metal over the barrier layer and extending to a top surface of the dielectric layer.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: February 28, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Derya Deniz, Benjamin G. Moser, Sunit S. Mahajan, Domingo A. Ferrer Luppi