Abstract: Embodiments for a metadata predictor. An index pipeline generates indices in an index buffer in which the indices are used for reading out a memory device. A prediction cache is populated with metadata of instructions read from the memory device. A prediction pipeline generates a prediction using the metadata of the instructions from the prediction cache, the populating of the prediction cache with the metadata of the instructions being performed asynchronously to the operating of the prediction pipeline.

Abstract: Embodiments include storing return addresses for a branch-target-buffer. Aspects include receiving a first instruction and based on a determination that the first instruction is a branch instruction and potentially a call, storing a return address associated with the branch instruction in a prediction return address table, wherein the prediction return address table includes an entry that corresponds to an index value that is created based on a target address of the first instruction, and wherein the entry includes the return address that is created based on an address of a sequential instruction of the first instruction. Aspects also include receiving a second instruction and based on a determination that the second instruction is predicted to be a return instruction with a predicted return address table index value from the branch-target-buffer, using the index value to select the return address to predict as the target address.

Abstract: Embodiments for a metadata predictor. An index pipeline generates indices in an index buffer in which the indices are used for reading out a memory device. A prediction cache is populated with metadata of instructions read from the memory device. A prediction pipeline generates a prediction using the metadata of the instructions from the prediction cache, the populating of the prediction cache with the metadata of the instructions being performed asynchronously to the operating of the prediction pipeline.

Abstract: A first example provides a circuit configured to operate in four modes. A first mode includes propagating data from a first terminal of the circuit to a second terminal of the circuit. A second mode includes propagating data from the second terminal of the circuit to the first terminal of the circuit. A third mode includes storing data received by the first terminal. A fourth mode includes storing data received by the second terminal. A second example provides a circuit configured to cause one or more communication links to operate in one of two modes based on data traffic detected on the one or more communication links. The first mode includes propagating data from a first router to a second router. The second mode includes propagating data to the first router from the second router.

Abstract: A first example provides a circuit configured to operate in four modes. A first mode includes propagating data from a first terminal of the circuit to a second terminal of the circuit. A second mode includes propagating data from the second terminal of the circuit to the first terminal. A fourth mode includes storing data received by the second terminal. A second example provides a circuit configured to cause one or more communication links to operate in one of two modes based on data traffic detected on the one or more communication links. The first mode includes propagating data from a first router to a second router. The second mode includes propagating data to the first router from the second router.