Abstract: A system may include electronic devices that communicate wirelessly. When positioned so that a pair of devices overlap or are adjacent to one another, the devices may operate in a linked mode. During linked operations, devices may communicate wirelessly while input gathering and content displaying operations are shared among the devices. One or both of a pair of devices may have sensors. A capacitive sensor or other sensor may be used to measure the relative position between two devices when the two devices overlap each other. Content displaying operations and other linked mode operations may be performed based on the measured relative position between the two devices and other information.

Abstract: A system may include electronic devices that communicate wirelessly. When positioned so that a pair of devices overlap or are adjacent to one another, the devices may operate in a linked mode. During linked operations, devices may communicate wirelessly while input gathering and content displaying operations are shared among the devices. One or both of a pair of devices may have sensors. A capacitive sensor or other sensor may be used to measure the relative position between two devices when the two devices overlap each other. Content displaying operations and other linked mode operations may be performed based on the measured relative position between the two devices and other information.

Abstract: A routing apparatus includes a PCB having first and second arrays of contact pads, an interposer having third, fourth and fifth arrays of contact pads, the third and fourth arrays of contact pads being disposed on opposing surfaces of the interposer, the third array of contact pads being electrically connected to the first array of contact pads. First and second integrated circuits are respectively mounted on the second and fourth arrays of contact pads. The interposer includes a first group of conductive traces insulated from one another, a first array of conductive vias extending perpendicularly to the first group of conductive traces, the first array of conductive vias including through-vias connecting the third array of contact pads to corresponding contact pads in the fourth array of contact pads.

Abstract: A circuit board includes conductive traces being sandwiched by an upper insulating layer and a lower insulating layer, a first array of conductive vias extending perpendicularly to the conductive traces, the vias in the first array of conductive vias being arranged such that any two adjacent vias in a row of vias extending along any given dimension in the first array of conductive vias are equally spaced from each other, and isolation resistors embedded within the first array of conductive vias such that each isolation resistor is disposed between at least two adjacent vias in the first array of conductive vias, each isolation resistor being disposed closer to the conductive via to which the isolation resistor is coupled than all other conductive vias surrounding the isolation resistor.

Abstract: A routing apparatus includes a PCB having first and second arrays of contact pads, an interposer having third, fourth and fifth arrays of contact pads, the third and fourth arrays of contact pads being disposed on opposing surfaces of the interposer, the third array of contact pads being electrically connected to the first array of contact pads. First and second integrated circuits are respectively mounted on the second and fourth arrays of contact pads. The interposer includes a first group of conductive traces insulated from one another, a first array of conductive vias extending perpendicularly to the first group of conductive traces, the first array of conductive vias including through-vias connecting the third array of contact pads to corresponding contact pads in the fourth array of contact pads.

Abstract: A circuit board includes conductive traces being sandwiched by an upper insulating layer and a lower insulating layer, a first array of conductive vias extending perpendicularly to the conductive traces, the vias in the first array of conductive vias being arranged such that any two adjacent vias in a row of vias extending along any given dimension in the first array of conductive vias are equally spaced from each other, and isolation resistors embedded within the first array of conductive vias such that each isolation resistor is disposed between at least two adjacent vias in the first array of conductive vias, each isolation resistor being disposed closer to the conductive via to which the isolation resistor is coupled than all other conductive vias surrounding the isolation resistor.

Abstract: A data storage device comprises at least one array of memory elements arranged in a plurality of rows and columns; coding means for coding an input data into a form having a balanced proportion of ‘1’s and ‘0’s, said coding means comprising means for applying an output of a pseudo random bit sequence generator to said incoming data, wherein the coded data is stored in the array of memory elements such that the ‘1’s and ‘0’s are spatially distributed relatively evenly across the plurality of memory elements; and decoding means for decoding the coded data read from the plurality of memory elements, into the original data.

Abstract: A magnetoresistive solid-state storage device (MRAM) performs error correction coding (ECC) of stored information. At manufacture or during use, each logical block of ECC encoded data and/or the corresponding set of storage cells are evaluated to determine suitability for continued use, or whether remedial action is necessary. In a first preferred method ECC decoding is attempted to determine whether information is unrecoverable from the block of ECC encoded data. In a second preferred method a parametric evaluation is made prior to attempting ECC decoding.

Abstract: A data storage device comprises at least one array of memory elements arranged in a plurality of rows and columns; coding means for coding an input data into a form having a balanced proportion of ‘1’s and ‘0’s, said coding means comprising means for applying an output of a pseudo random bit sequence generator to said incoming data, wherein the coded data is stored in the array of memory elements such that the ‘1’s and ‘0’s are spatially distributed relatively evenly across the plurality of memory elements; and decoding means for decoding the coded data read from the plurality of memory elements, into the original data.