Patents by Inventor Dominic S. Suryabudi
Dominic S. Suryabudi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11543974Abstract: A data storage subsystem is disclosed that implements a process for storing and/or reconstructing system data, such as a system mapping table. In certain embodiments, table pages are systematically copied, or flushed, to non-volatile memory in a progressive manner, according to a fixed ratio of flushed table pages per table update trigger, thereby facilitating write and/or load efficiency. Full or partial reconstruction of a table may be performed within a bounded number of operations based on the size of the table, the ratio implemented, and/or other characteristics.Type: GrantFiled: January 20, 2021Date of Patent: January 3, 2023Assignee: Western Digital Technologies, Inc.Inventors: Jerry Lo, Dominic S. Suryabudi, Lan D. Phan
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Publication number: 20210141543Abstract: A data storage subsystem is disclosed that implements a process for storing and/or reconstructing system data, such as a system mapping table. In certain embodiments, table pages are systematically copied, or flushed, to non-volatile memory in a progressive manner, according to a fixed ratio of flushed table pages per table update trigger, thereby facilitating write and/or load efficiency. Full or partial reconstruction of a table may be performed within a bounded number of operations based on the size of the table, the ratio implemented, and/or other characteristics.Type: ApplicationFiled: January 20, 2021Publication date: May 13, 2021Inventors: Jerry LO, Dominic S. SURYABUDI, Lan D. PHAN
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Patent number: 10942656Abstract: A data storage subsystem is disclosed that implements a process for storing and/or reconstructing system data, such as a system mapping table. In certain embodiments, table pages are systematically copied, or flushed, to non-volatile memory in a progressive manner, according to a fixed ratio of flushed table pages per table update trigger, thereby facilitating write and/or load efficiency. Full or partial reconstruction of a table may be performed within a bounded number of operations based on the size of the table, the ratio implemented, and/or other characteristics.Type: GrantFiled: July 26, 2019Date of Patent: March 9, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Jerry Lo, Dominic S. Suryabudi, Lan D. Phan
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Publication number: 20190347017Abstract: A data storage subsystem is disclosed that implements a process for storing and/or reconstructing system data, such as a system mapping table. In certain embodiments, table pages are systematically copied, or flushed, to non-volatile memory in a progressive manner, according to a fixed ratio of flushed table pages per table update trigger, thereby facilitating write and/or load efficiency. Full or partial reconstruction of a table may be performed within a bounded number of operations based on the size of the table, the ratio implemented, and/or other characteristics.Type: ApplicationFiled: July 26, 2019Publication date: November 14, 2019Inventors: Jerry LO, Dominic S. SURYABUDI, Lan D. PHAN
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Patent number: 10379755Abstract: A data storage subsystem is disclosed that implements a process for storing and/or reconstructing system data, such as a system mapping table. In certain embodiments, table pages are systematically copied, or flushed, to non-volatile memory in a progressive manner, according to a fixed ratio of flushed table pages per table update trigger, thereby facilitating write and/or load efficiency. Full or partial reconstruction of a table may be performed within a bounded number of operations based on the size of the table, the ratio implemented, and/or other characteristics.Type: GrantFiled: October 26, 2015Date of Patent: August 13, 2019Assignee: Western Digital Technologies, Inc.Inventors: Jerry Lo, Dominic S. Suryabudi, Lan D. Phan
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Patent number: 9977612Abstract: A data storage system is disclosed that utilizes garbage collection and logs for managing system data. In one embodiment, system data stored in a non-volatile memory is updated based on the character of changes to data stored in a data storage system (e.g., changes caused by host system activity). For example, when changes to stored data are scattered (e.g., changes are made to random memory locations), it may be beneficial to generate and accumulate more logs reflecting changes to the system data. As another example, when changes to stored data are substantially consolidated (e.g., changes are made to consecutive memory locations), it may be beneficial to update system data stored in the non-volatile memory more frequently. Reduction in write amplification, increase in efficiency, and reduction in start-up and initialization time can be attained. Reconstruction time of system data can also be reduced.Type: GrantFiled: May 11, 2012Date of Patent: May 22, 2018Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Jerry Lo, Dominic S. Suryabudi
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Publication number: 20160048352Abstract: A data storage subsystem is disclosed that implements a process for storing and/or reconstructing system data, such as a system mapping table. In certain embodiments, table pages are systematically copied, or flushed, to non-volatile memory in a progressive manner, according to a fixed ratio of flushed table pages per table update trigger, thereby facilitating write and/or load efficiency. Full or partial reconstruction of a table may be performed within a bounded number of operations based on the size of the table, the ratio implemented, and/or other characteristics.Type: ApplicationFiled: October 26, 2015Publication date: February 18, 2016Inventors: Jerry LO, Dominic S. SURYABUDI, Lan D. PHAN
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Patent number: 9170932Abstract: A data storage subsystem is disclosed that implements a process for storing and/or reconstructing system data, such as a system mapping table. In certain embodiments, table pages are systematically copied, or flushed, to non-volatile memory in a progressive manner, according to a fixed ratio of flushed table pages per table update trigger, thereby facilitating write and/or load efficiency. Full or partial reconstruction of a table may be performed within a bounded number of operations based on the size of the table, the ratio implemented, and/or other characteristics.Type: GrantFiled: May 22, 2012Date of Patent: October 27, 2015Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Jerry Lo, Dominic S. Suryabudi, Lan D. Phan
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Patent number: 8938583Abstract: Embodiments of the invention are directed to systems and methods for optimizing data access request handling in a non-volatile memory (NVM) device. In one embodiment, the device may include a number of storage elements that can be concurrently programmed, and the device may include a controller that determines whether data access requests may be staged and processed together so that the concurrency of the storage device may be optimized. In one embodiment, staged requests are selectively combined together so that their combined data size is greater than or equal to a data size that can be programmed in a single set of concurrent operations to the storage elements.Type: GrantFiled: November 16, 2011Date of Patent: January 20, 2015Assignee: Western Digital Technologies, Inc.Inventor: Dominic S. Suryabudi
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Patent number: 8924627Abstract: A flash memory device is disclosed comprising a flash controller for accessing a first flash memory over a first channel and a second flash memory over a second channel. A multi-command descriptor block is received from a host, wherein the multi-command descriptor block comprises identifiers for identifying a plurality of access commands that the host is preparing to request. A first group of the access commands are selected to execute concurrently and a second group of the access commands are selected to execute concurrently. The first group of access commands are received from the host and executed concurrently by accessing at least the first and second flash memories concurrently. The second group of access commands are received from the host and executed concurrently by accessing at least the first and second flash memories concurrently.Type: GrantFiled: March 28, 2011Date of Patent: December 30, 2014Assignee: Western Digital Technologies, Inc.Inventors: Mei-Man L. Syu, Robert L. Horn, Virgil V. Wilkins, Dominic S. Suryabudi
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Patent number: 8769232Abstract: A non-volatile semiconductor memory module is disclosed comprising a memory device and memory controller operably coupled to the memory device, wherein the memory controller is operable to receive a host command, split the host command into one or more chunks comprising a first chunk comprising at least one logical block address (LBA), and check the first chunk against an active chunk coherency list comprising one or more active chunks to determine whether the first chunk is an independent chunk, and ready to be submitted for access to the memory device, or a dependent chunk, and deferred access to the memory device until an associated dependency is cleared.Type: GrantFiled: April 6, 2011Date of Patent: July 1, 2014Assignee: Western Digital Technologies, Inc.Inventors: Dominic S. Suryabudi, Mei-Man L. Syu
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Patent number: 8458435Abstract: Embodiments of the invention are directed to systems and methods for detecting sequential write threads in non-volatile storage media. The embodiments described herein detect write commands directed to a range of logical addresses corresponding to a write thread. Upon detection of a write command directed to a write thread, the write command is assigned a physical write address associated with the write thread. Identification of write threads can be implemented with a hardware component which performs comparison operations between the write command address range and the write thread address range.Type: GrantFiled: December 20, 2010Date of Patent: June 4, 2013Assignee: Western Digital Technologies, Inc.Inventors: Charles P. Rainey, III, Dominic S. Suryabudi, Ho-Fan Kang
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Patent number: 8316176Abstract: A non-volatile semiconductor memory is disclosed comprising a memory device including a memory array having a plurality of blocks, each block comprising a plurality of memory segments. A plurality of logical block address (LBA) ranges are defined each identifying a plurality of LBA addresses, wherein at least one block is assigned to each LBA range. A plurality of write commands are received from a host, wherein each write command identifies at least one LBA. Data is written for each write command to the memory device. During a garbage collection operation, a memory segment storing valid write data is identified to be relocated, and the valid write data is relocated to a memory segment in a block of the corresponding LBA range.Type: GrantFiled: February 17, 2010Date of Patent: November 20, 2012Assignee: Western Digital Technologies, Inc.Inventors: Lan D. Phan, Dominic S. Suryabudi
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Publication number: 20120260020Abstract: A non-volatile semiconductor memory module is disclosed comprising a memory device and memory controller operably coupled to the memory device, wherein the memory controller is operable to receive a host command, split the host command into one or more chunks comprising a first chunk comprising at least one logical block address (LBA), and check the first chunk against an active chunk coherency list comprising one or more active chunks to determine whether the first chunk is an independent chunk, and ready to be submitted for access to the memory device, or a dependent chunk, and deferred access to the memory device until an associated dependency is cleared.Type: ApplicationFiled: April 6, 2011Publication date: October 11, 2012Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: DOMINIC S. SURYABUDI, MEI-MAN L. SYU
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Publication number: 20120254504Abstract: A flash memory device is disclosed comprising a flash controller for accessing a first flash memory over a first channel and a second flash memory over a second channel. A multi-command descriptor block is received from a host, wherein the multi-command descriptor block comprises identifiers for identifying a plurality of access commands that the host is preparing to request. A first group of the access commands are selected to execute concurrently and a second group of the access commands are selected to execute concurrently. The first group of access commands are received from the host and executed concurrently by accessing at least the first and second flash memories concurrently. The second group of access commands are received from the host and executed concurrently by accessing at least the first and second flash memories concurrently.Type: ApplicationFiled: March 28, 2011Publication date: October 4, 2012Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Mei-Man L. Syu, Robert L. Horn, Virgil V. Wilkins, Dominic S. Suryabudi