Patents by Inventor Dominicus Martinus Wilhelmus Leenaerts
Dominicus Martinus Wilhelmus Leenaerts has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130028352Abstract: A down-converter for receiving a multiband radio frequency signal (RF) and a local oscillator signal comprises a frequency divider and a heterodyne receive chain. The frequency divider is configured to divide the local oscillator signal and provide different divided local oscillator signals. The heterodyne receive chain comprises a first stage mixer and second stage mixers. The first stage mixer is configured to mix the multiband radio frequency signal and either the local oscillator signal or a divided local oscillator signal to generate a first intermediate frequency signal. Each second stage mixer is configured to mix the first intermediate signal and a divided local oscillator signal to generate second intermediate frequency signals that each represent a band from the multiband radio frequency signal. The frequency divider is configured to provide a different divided local oscillator signal to each of the second stage mixers.Type: ApplicationFiled: July 25, 2012Publication date: January 31, 2013Applicant: NXP B.V.Inventors: Dominicus Martinus Wilhelmus LEENAERTS, Gerben Willem DE JONG, Edwin VAN DER HEIJDEN, Marcellinus Johannes Maria GEURTS
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Publication number: 20120139587Abstract: A low power frequency synthesiser circuit (30) for a radio transceiver, the synthesiser circuit comprising: a digital controlled oscillator (33) configured to generate an output signal (F0) having a frequency controlled by an input digital control word (DCW); a feedback loop (35-38) connected between an output and an input of the digital controlled oscillator, the feedback loop configured to provide the digital control word to the input of the digital controlled oscillator from an error derived from an input frequency control word (FCW) and the output signal; and a duty cycle module (32) connected to the digital controlled oscillator and the feedback loop, the duty cycle module configured to generate a plurality of control signals to periodically enable and disable the digital controlled oscillator for a set fraction of clock cycles of an input reference clock signal (RefClock).Type: ApplicationFiled: March 30, 2010Publication date: June 7, 2012Applicant: NXP B.V.Inventors: Salvatore Drago, Fabio Sebastiano, Dominicus Martinus Wilhelmus Leenaerts, Lucien Johannes Breems, Bram Nauta
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Patent number: 8145176Abstract: A front end and a high frequency receiver (1) provided therewith are described, which front end comprises a quadrature low noise amplifier (2-1, 2-2) as a low noise amplifier. A high isolation between local oscillators (6-1, 6-2) and quadrature mixers (3-1, 3-2) is achieved thereby, reducing a DC offset at mixer outputs (7, 8). The quadrature low noise amplifier may be implemented as a differential class AB cascade arrangement of MOST or FET semiconductors (15). A low distortion receiver (1) having a high linearity is the result.Type: GrantFiled: May 26, 2010Date of Patent: March 27, 2012Assignee: ST-Ericsson SAInventors: Eise Carel Dijkmans, Dominicus Martinus Wilhelmus Leenaerts, Petrus Gerardus Maria Baltus
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Publication number: 20110134964Abstract: A frequency generating arrangement for generation of at least two predetermined frequencies is introduced. The arrangement comprises a phase locked loop circuit with at least two control value storage units and at least one controlled oscillator unit, wherein the control value storage units being configured to selectively output a control signal to the at least one voltage controlled oscillator unit, causing generation of one of the at least two predetermined frequencies. Frequency generating system for generation of ultra-fast hopping-frequency sequences comprises at least a first and a second frequency generating arrangement and further a controlling unit and a multiplexer unit for selectively connecting only one of the outputs of the two frequency generating arrangements with an output of the system.Type: ApplicationFiled: August 12, 2009Publication date: June 9, 2011Applicant: NXP B.V.Inventors: Remco Cornelis Herman van de Beek, Dominicus Martinus Wilhelmus Leenaerts
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Publication number: 20100240336Abstract: A front end and a high frequency receiver (1) provided therewith are described, which front end comprises a quadrature low noise amplifier (2-1, 2-2) as a low noise amplifier. A high isolation between local oscillators (6-1, 6-2) and quadrature mixers (3-1, 3-2) is achieved thereby, reducing a DC offset at mixer outputs (7, 8). The quadrature low noise amplifier may be implemented as a differential class AB cascade arrangement of MOST or FET semiconductors (15). A low distortion receiver (1) having a high linearity is the result.Type: ApplicationFiled: May 26, 2010Publication date: September 23, 2010Inventors: Eise Carel Dijkmans, Dominicus Martinus Wilhelmus Leenaerts, Petrus Gerardus Maria Baltus
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Patent number: 7787847Abstract: A front end and a high frequency receiver provided therewith are described, which front end comprises a quadrature low noise amplifier as a low noise amplifier. A high isolation between local oscillators and quadrature mixers is achieved thereby, reducing a DC offset at mixer outputs. The quadrature low noise amplifier may be implemented as a differential class AB cascode arrangement of MOST or FET semiconductors. A low distortion receiver having a high linearity is the result.Type: GrantFiled: January 23, 2002Date of Patent: August 31, 2010Assignee: ST-Ericsson SAInventors: Eise Carel Dijkmans, Dominicus Martinus Wilhelmus Leenaerts, Petrus Gerardus Maria Baltus
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Patent number: 7755444Abstract: The present invention relates to a polar modulation apparatus and method, in which an in-phase and a quadrature-phase signal are processed in the analog domain to generate an analog signal corresponding to a derivative of a phase component of said polar-modulated signal. The analog signal is then input to a control input of a controlled oscillator (40). As an example, the processing may be based on a differentiate-and-multiply algorithm in the analog domain. Thereby, phase and envelope signals are generated in the analog domain and bandwidth enlargement due to the processing of the polar signals and corresponding aliasing can be prevented to obtain a highly accurate polar-modulated output signal.Type: GrantFiled: October 18, 2006Date of Patent: July 13, 2010Assignee: ST-Ericsson SAInventors: Paul Mattheijssen, Dominicus Martinus Wilhelmus Leenaerts
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Patent number: 7737738Abstract: A frequency divider comprising, a first latch circuit and a second latch circuit, the second latch circuit being crossed-coupled to the first latch circuit. Each latch comprises a respective sense amplifier coupled to a respective latch. The sense amplifiers comprise a first clock input for receiving a first clock signal. The latches comprise a second clock input for receiving a second clock signal having a second frequency, the second frequency being substantially double the first frequency.Type: GrantFiled: July 27, 2005Date of Patent: June 15, 2010Assignee: ST-Ericsson SAInventors: Mustafa Acar, Dominicus Martinus Wilhelmus Leenaerts, Bram Nauta
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Patent number: 7671641Abstract: A frequency divider includes a first latch and a second latch. The first latch is configured to receive a clock signal. The first latch is cross-coupled to the second latch. The second latch includes a circuit configured as a low-pass filter. The second latch further includes a differential pair of transistors. Each of the transistors include a drain, a source and a gate. The gates of the at least two transistors configured to receive a signal generated by the first latch. Additionally, the gates of the at least two other transistors are coupled to a control signal for determining a low-pass characteristic of the second latch.Type: GrantFiled: March 4, 2005Date of Patent: March 2, 2010Assignee: ST-Ericsson SAInventors: Mustafa Acar, Dominicus Martinus Wilhelmus Leenaerts, Bram Nauta
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Publication number: 20090304044Abstract: A frequency-hopping arrangement comprises a basic-frequency branch (DIV1), an offset-frequency branch (DIV2, DIV3, SCC), and a controllable frequency converter (SBM, FSC). The basic-frequency branch (DIV1) receives an oscillator signal (OS) having an oscillator-signal frequency (7920 MHz). The basic-frequency branch has a frequency-division factor (/2) so as to provide a basic-frequency signal (BF) having a basic frequency (+3960 MHz) that is the oscillator-signal frequency divided by the frequency-division factor. The offset-frequency branch (DIV2, DIV3, SCC) receives the same oscillator signal (OS). The offset-frequency branch has a different frequency-division factor (/3, /5) so as to provide an offset-frequency signal (OF) having an offset frequency (+528 MHz) that is the oscillator-signal frequency divided by the different frequency-division factor.Type: ApplicationFiled: January 10, 2006Publication date: December 10, 2009Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.Inventors: Remco Cornelis Herman Van De Beek, Dominicus Martinus Wilhelmus Leenaerts
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Patent number: 7605733Abstract: A radio-frequency ??-modulator comprises a first mixer in the forward path for down-converting the signals in this forward path with a local oscillator frequency and a second mixer in the feedback path for up-converting the feedback signal with the same local oscillator frequency. Delays between the two mixing operations cause a loss of gain in the loop of the ??-modulator. An adjustable amplifier in the feedback path compensates for this loss of gain.Type: GrantFiled: December 11, 2006Date of Patent: October 20, 2009Assignee: NXP B.V.Inventors: Lucien Johannes Breems, Dominicus Martinus Wilhelmus Leenaerts
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Patent number: 7579883Abstract: A frequency divider providing an odd integer division factor comprising a binary counter (10) providing an even integer division factor, which is the first even number smaller than the odd division factor, the binary counter having a clock input for receiving a periodical clock signal (Ck) having a frequency. The circuit further comprises an end of count circuit (20) coupled to the binary counter and generating an End Of Count signal (EOC) for a clock (Ck) period after every even integer number periods of the clock signal (Ck), the end of count signal (EOC) being inputted to an input (IN) of the counter (10). The circuit further includes an output generator (30) coupled to the binary counter and to the clock signal (Ck), the output generator (30) generating an output signal (OUT) having a frequency which is substantially equal with the frequency of the frequency signal (Ck) divided by the odd division factor.Type: GrantFiled: July 27, 2005Date of Patent: August 25, 2009Assignee: NXP B.V.Inventors: Prashant Dekate, Dominicus Martinus Wilhelmus Leenaerts
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Patent number: 7567131Abstract: Devices (1) for exchanging ultra wide band signals comprise frequency translating stages (20,30) for frequency translating signals and oscillating stages (40) for supplying main inphase/quadrature oscillation signals to the frequency translating stages (20,30). By providing the oscillating stages (40) with polyphase filters (43,44) for reducing harmonics in oscillation signals, the main oscillation signals will be sufficiently clean. The oscillating stages (40) comprise mixers (46) for converting first inphase/quadrature oscillation signals and second inphase/quadrature oscillation signals into the main oscillation signals. The polyphase filters (43,44) may be located before and after the mixers (46). Frequency selectors (45) replace prior art multiplexers located after the mixers (46).Type: GrantFiled: September 5, 2005Date of Patent: July 28, 2009Assignee: Koninklijke Philips Electronics N.V.Inventors: Remco Cornelis Herman Van De Beek, Dominicus Martinus Wilhelmus Leenaerts, Gerard Van Der Weide, Jozef Reinerus Maria Bergervoet
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Patent number: 7558361Abstract: A phase-switching dual modulus prescaler having a dual modulus divider is provided. Said divider comprises a first and second divide-by-2 circuit (A;B), wherein said second divide-by-2 circuit (B) is coupled to the output of said first divide-by-2 circuit (A) and at least said second divide-by-two circuit (B) comprises a four phase output each separated by 90°. A phase selection unit (PSU) is provided for selecting one of the four phase outputs (Ip, In, Qp, Qn; INi, INni, INq, Innq) of the second divide-by-2 circuit (B). Moreover, a phase control unit is provided for providing control signal (C1, NC0; C2, NC2; C3, NC3) to the phase selection unit, wherein the phase selection unit (PSU) performs the selection of the four phase outputs (Ip, In, Qp, Qn; INi, INni, INq, Innq) according to the control signals (C0, NC0; C1, NC1; C2, NC2). Said phase selection unit (PSU) is implemented based on direct logic.Type: GrantFiled: September 28, 2004Date of Patent: July 7, 2009Assignee: ST Wireless SAInventors: Dominicus Martinus Wilhelmus Leenaerts, Nenad Pavlovic, Ketan Mistry
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Patent number: 7483681Abstract: A transmitter comprises a power amplifier which has an amplifier power-supply input and an output to supply a transmission signal with an output power. A power supply has power supply outputs to supply a first power supply voltage and a second power supply voltage. A switching circuit is arranged between the power supply outputs and the amplifier power-supply input. A controller has an input to receive a power change command to control: first the switching circuit to supply the first power supply voltage to the amplifier power-supply input, and the power supply to vary a level of the second power supply voltage, the level of the second power supply voltage being lower or higher than a level of the first power supply voltage if the power change command indicates that the output power has to decrease or increase, respectively, and secondly the switching circuit to supply the second power supply voltage to the amplifier power-supply input.Type: GrantFiled: January 29, 2008Date of Patent: January 27, 2009Assignee: NXP, B.V.Inventors: Giuseppe Grillo, Pepijn Willebrord Justinus Van De Ven, Pieter Gerrit Blanken, Dominicus Martinus Wilhelmus Leenaerts, Franciscus Adrianus Cornelis Maria Schoofs
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Patent number: 7466785Abstract: A Phase Locked Loop (1) comprising a frequency detector (10) including a balanced quadricorrelator (2), the loop (1) being characterized in that the quadricorrelator (2) comprises double edge clocked bi-stable circuits (21, 22, 23, 24, 25, 26, 27, 28) coupled to multiplexers (31, 32, 33, 34) being controlled by a signal having the same bitrate as the incoming D signal (D).Type: GrantFiled: October 8, 2003Date of Patent: December 16, 2008Assignee: NXP B.V.Inventors: Mihai Adrian Tiberiu Sanduleanu, Dominicus Martinus Wilhelmus Leenaerts
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Publication number: 20080266015Abstract: The present invention relates to a polar modulation apparatus and method, in which an in-phase and a quadrature-phase signal are processed in the analog domain to generate an analog signal corresponding to a derivative of a phase component of said polar-modulated signal. The analog signal is then input to a control input of a controlled oscillator (40). As an example, the processing may be based on a differentiate-and-multiply algorithm in the analog domain. Thereby, phase and envelope signals are generated in the analog domain and bandwidth enlargement due to the processing of the polar signals and corresponding aliasing can be prevented to obtain a highly accurate polar-modulated output signal.Type: ApplicationFiled: October 18, 2006Publication date: October 30, 2008Applicant: NXP B.V.Inventors: Paul Matteijssen, Dominicus Martinus Wilhelmus Leenaerts
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Publication number: 20080265953Abstract: A frequency divider comprising, a first latch circuit (10) and a second latch circuit (10), the second latch circuit (10?) being crossed-coupled to the first latch circuit (10). Each latch (10; 10?) comprises a respective sense amplifier coupled to a respective latch (11). The sense amplifiers comprise a first clock input for receiving a first clock signal (f, f) and 5 respective complementary first clock signal having a first frequency. The latches (11) comprise a second clock input (2f; 2f) for receiving a second clock signal and respective complementary second clock signal having a second frequency, the second frequency being substantially double the first frequency.Type: ApplicationFiled: July 27, 2005Publication date: October 30, 2008Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Mustafa Acar, Dominicus Martinus Wilhelmus Leenaerts, Bram Nauta
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Publication number: 20080186062Abstract: A frequency divider providing an odd integer division factor comprising a binary counter (10) providing an even integer division factor, which is the first even number smaller than the odd division factor, the binary counter having a clock input for receiving a periodical clock signal (Ck) having a frequency. The circuit further comprises an end of count circuit (20) coupled to the binary counter and generating an End Of Count signal (EOC) for a clock (Ck) period after every even integer number periods of the clock signal (Ck), the end of count signal (EOC) being inputted to an input (IN) of the counter (10).Type: ApplicationFiled: July 27, 2005Publication date: August 7, 2008Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Prashant Dekate, Dominicus Martinus Wilhelmus Leenaerts
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Patent number: 7392023Abstract: A transmitter comprises a power amplifier (PA) which has an amplifier powersupply input (PI) and an output (PAO) to supply a transmission signal (Vo) with an output power (Po). A power supply (PS) has power supply outputs (PSO1, PSO2) to supply a first power supply voltage (PV1) and a second power supply voltage (PV2). A switching circuit(SC) is arranged between the power supply outputs (PSO 1, PSO2) and the amplifier powersupply input (PI).Type: GrantFiled: March 22, 2004Date of Patent: June 24, 2008Assignee: NXP B.V.Inventors: Giuseppe Grillo, Pepijn Van De Ven, Pieter Blanken, Dominicus Martinus Wilhelmus Leenaerts, Franciscus Adrianus Cornelis Maria Schoofs