Abstract: A method of via formation including forming a sacrificial mask over a conductive layer, forming a plurality of pillars in the sacrificial mask and the conductive layer, wherein each pillar of the plurality of pillars includes a sacrificial cap and a first conductive via, depositing a spacer between the plurality of pillars, masking at least one of the sacrificial caps, removing at least one of the sacrificial caps to create openings, forming second conductive vias in the openings, and depositing a dielectric coplanar to a top surface of the second conductive vias.

Abstract: A semiconductor device is provided. The semiconductor device includes an interlayer dielectric layer; and a plurality of metal contacts formed in the interlayer dielectric layer. The plurality of metal contacts include a plurality of shallow metal contacts having a first depth, and a plurality of deep metal contacts having a second depth that is greater than the first depth, wherein a first one of the shallow metal contacts overlaps and directly contacts a first one of the deep metal contacts, and wherein the plurality of metal contacts have an equal spacing therebetween.

Abstract: A semiconductor structure including a dielectric isolation region between and electrical isolating a first top contact of a first stacked transistor from a second top contact of a second stacked transistor, where at least one vertical surface of the first top contact is substantially flush with at least one vertical surface of the isolation region, and where at least one vertical surface of the second top contact is substantially flush with the at least one vertical surface of the isolation region.

Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for placing self-aligned top vias at line ends of an interconnect structure. In a non-limiting embodiment of the invention, a line feature is formed in a metallization layer of an interconnect structure. The line feature can include a line hard mask. A trench is formed in the line feature to expose line ends of the line feature. The trench is filled with a host material and a growth inhibitor is formed over a first line end of the line feature. A via mask is formed over a second line end of the line feature. The via mask can be selectively grown on an exposed surface of the host material. Portions of the line feature that are not covered by the via mask are recessed to define a self-aligned top via at the second line end.

Abstract: A method for fabricating a semiconductor device includes forming a conductive shell layer along a memory stack and a patterned hardmask disposed on the memory stack, and etching the patterned hardmask, the conductive shell layer and the memory stack to form a structure including a central core surrounded by a conductive outer shell disposed on a patterned memory stack.

Abstract: Various embodiments herein relate to methods, apparatus, and systems that utilize a multi-layer hardmask in the context of patterning a semiconductor substrate using extreme ultraviolet photoresist. The multi-layer hardmask includes (1) an upper layer that includes a metal-containing material such as a metal oxide, a metal nitride, or a metal oxynitride, and (2) a lower layer that includes an inorganic dielectric silicon-containing material. Together, these layers of the multi-layer hardmask provide excellent etch selectivity and reduce formation of defects such as microbridges and line breaks. Certain embodiments relate to deposition of the multi-layer hardmask. Other embodiments relate to etching of the multi-layer hardmask. Some embodiments involve both deposition and etching of the multi-layer hardmask.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a plurality of metal lines on substrate, forming a sacrificial dielectric material layer between the metal lines, forming a hardmask over at least one of the metal lines, etching at least one of the metal lines that is not covered by the hardmask, treating the sacrificial dielectric material layer to soften the layer. The method also includes removing the treated sacrificial dielectric material layer.

Abstract: A memory device with modified top electrode contact includes a memory pillar composed of a bottom electrode, a magnetic random-access memory (MRAM) stack above the bottom electrode, and a top electrode above the MRAM stack. A first portion of an encapsulation layer is disposed along opposite sidewalls of the bottom electrode, on opposite sidewalls of the MRAM stack and on opposite sidewalls of a bottom portion of the top electrode, a second portion of the encapsulation layer is located above a second dielectric layer. A metal cap is located above an uppermost surface and opposite sidewalls of a top portion of the top electrode and above an uppermost surface of the first portion of the encapsulation layer. A second conductive interconnect is formed above a top surface of the metal cap wrapping around opposite sidewalls of the first portion of the encapsulation layer and opposite sidewalls of the metal cap.

Abstract: A method of making a back-end-of-line (BEOL) component includes filling spaces in a layer of metal material and a layer of hardmask material with a layer of scaffolding material. The method further includes forming at least one plug on top of the layer of metal material such that the at least one plug is integrally formed with the layer of scaffolding material. The method further includes removing the layer of hardmask material such that a top surface of the layer of metal material is exposed except where the at least one plug is formed on top of the layer of metal material. The method further includes recessing the layer of metal material where the top surface of the layer of metal material is exposed. The method further includes removing the scaffolding material.

Abstract: A method of via formation including forming a sacrificial mask over a conductive layer, forming a plurality of pillars in the sacrificial mask and the conductive layer, wherein each pillar of the plurality of pillars includes a sacrificial cap and a first conductive via, depositing a spacer between the plurality of pillars, masking at least one of the sacrificial caps, removing at least one of the sacrificial caps to create openings, forming second conductive vias in the openings, and depositing a dielectric coplanar to a top surface of the second conductive vias.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a plurality of metal lines on substrate, forming a sacrificial dielectric material layer between the metal lines, forming a hardmask over at least one of the metal lines, etching at least one of the metal lines that is not covered by the hardmask, treating the sacrificial dielectric material layer to soften the layer. The method also includes removing the treated sacrificial dielectric material layer.

Abstract: A method for fabricating a semiconductor device includes recessing a first odd hardmask and a first even hardmask to form recessed odd and even hardmasks, forming a first conductive hardmask including first conductive hardmask material on the recessed odd hardmask and a second conductive hardmask on the recessed even hardmask, and forming self-aligned vias at line ends corresponding to the first odd and even conductive lines based at least in part on the first and second conductive hardmasks.

Abstract: Methods of patterning vias and trenches using a polymerization protective liner after forming a lower patterned mask layer used for etching trenches on a semiconductor substrate prior to forming an upper patterned mask layer used for etching vias are provided. Methods involve forming a polymerization protective liner either nonconformally or conformally using silicon tetrachloride and methane polymerization. Polymerization protective liners may be sacrificial.

Abstract: Methods and structures for forming vias are provided. The method includes forming a structure that includes an odd line hardmask and an even line hardmask. The odd line hardmask and the even line hardmask include different hardmask materials that have different etch selectivity with respect to each other. The method includes patterning vias separately into the odd line hardmask and the even line hardmask based on the different etch selectivity of the different hardmask materials. The method also includes forming via plugs at the vias. The method includes cutting even line cuts and odd line cuts into the structure. The even line cuts and the odd line cuts are self-aligned with the vias. The vias are formed at line ends of the structure.

Abstract: A method for fabricating a semiconductor device includes forming a conductive shell layer along a memory stack and a patterned hardmask disposed on the memory stack, and etching the patterned hardmask, the conductive shell layer and the memory stack to form a structure including a central core surrounded by a conductive outer shell disposed on a patterned memory stack.

Abstract: Methods and structures for forming vias are provided. The method includes forming a structure that includes an odd line hardmask and an even line hardmask. The odd line hardmask and the even line hardmask include different hardmask materials that have different etch selectivity with respect to each other. The method includes patterning vias separately into the odd line hardmask and the even line hardmask based on the different etch selectivity of the different hardmask materials. The method also includes forming via plugs at the vias. The method includes cutting even line cuts and odd line cuts into the structure. The even line cuts and the odd line cuts are self-aligned with the vias. The vias are formed at line ends of the structure.

Abstract: Methods and structures for improving alignment contrast for patterning a metal layer generally includes depositing a metal layer having a plurality of grains, wherein grain boundaries between the grains forms grooves at a surface of the metal layer. The metal layer is subjected to surface treatment to form an oxide or a nitride layer and fill the surface grooves. The metal layer can be patterned using alignment marks in the metal layer and/or underlying layers. Filling the grooves with the oxide or nitride increases alignment contrast relative to patterning the metal layer without the surface treating.

Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for placing self-aligned top vias at line ends of an interconnect structure. In a non-limiting embodiment of the invention, a line feature is formed in a metallization layer of an interconnect structure. The line feature can include a line hard mask. A trench is formed in the line feature to expose line ends of the line feature. The trench is filled with a host material and a growth inhibitor is formed over a first line end of the line feature. A via mask is formed over a second line end of the line feature. The via mask can be selectively grown on an exposed surface of the host material. Portions of the line feature that are not covered by the via mask are recessed to define a self-aligned top via at the second line end.

Abstract: A method is presented for preventing excessive cap dielectric loss in memory areas and logic areas of a device. The method includes forming a first conductive line with top via and a conductive pad over a dielectric layer, wherein the conductive pad includes a microstud, depositing a dielectric cap in direct contact with the first conductive line and the conductive pad, and constructing a top electrode, a magnetic tunnel junction (MTJ) stack, and a bottom electrode in vertical alignment with the microstud of the conductive pad.

Abstract: A method for fabricating a semiconductor device includes forming a conductive shell layer along a memory stack and a patterned hardmask disposed on the memory stack, and etching the patterned hardmask, the conductive shell layer and the memory stack to form a structure including a central core surrounded by a conductive outer shell disposed on a patterned memory stack.