Abstract: This application describes a peripheral cell structure for VLSI chips that requires the use of standard cells having both input and output capability connected to nearly all of the signal carrying pins. The cells function is alterable (to input or output and to where the data input signals originate) by control signals which may originate with a control register. The clock input signal is split into two independent signals to selectively disable the input or output registers, thus allowing the control register to be changed without affecting the contents of the other two registers. An early signal is also provided to prepare for mode changes.

Abstract: This application teaches that more accurate measurements of clock skew can be had by providing a clock monitor pin directly connected to the clock bus internal to the VLSI chip.

Abstract: Sequential faults are not tested for adequately when using test input operands generated in the chip from a random number generator to test the logic circuits in a very large scale integrated (VLSI) chip. Accordingly this application teaches the efficient construction of a test operand generator, using an input register with properly randomized feedback to break up sequential patterns which would otherwise develop in the input register.