Abstract: A redundant clock system for use in a computer is provided including a first oscillator which produces first reference clock signals; a second oscillator which produces second reference clock signals; a third oscillator which produces third reference clock signals; a first multiplexer which receives the first, second and third reference clock signals from the first, second and third oscillators and which provides a designated one of the received reference clock signals as a selected reference clock signal; a second multiplexer which receives the first, second and third reference clock signals from the first, second and third oscillators and which provides a designated one of the received reference clock signals as a selected reference clock signal; a third multiplexer which receives the first, second and third reference clock signals from the first, second and third oscillators and which provides a designated one of the received reference clock signals as a selected reference clock signal; a first phase-locke

Abstract: A fault tolerant computer system is provided which includes a first system module with a first processor and a first processor bus and a first I/O bus; a second system module with a second processor and a second processor bus and a second I/O bus; a third system module with a third processor and a third processor bus and a third I/O bus; wherein the first system module further includes a first control device which coordinates transfer of first transaction information between the first processor bus and each of the first I/O bus or the second I/O bus or the third I/O bus; and wherein the first system module includes first comparison logic which compares first transaction information with corresponding second transaction information; wherein the second system module further includes a second control device which coordinates transfer of second transaction information between the second processor bus and each of the first I/O bus or the second I/O bus or the third I/O bus; and wherein the second system module inc

Abstract: A fault tolerant computer system is provided which includes a first system module with a first processor and a first processor bus and a first I/O bus; a second system module with a second processor and a second processor bus and a second I/O bus; a third system module with a third processor and a third processor bus and a third I/O bus; wherein the first system module further includes a first control device which coordinates transfer of first transaction information between the first processor bus and each of the first I/O bus or the second I/O bus or the third I/O bus; and wherein the first system module includes first comparison logic which compares first transaction information with corresponding second transaction information; wherein the second system module further includes a second control device which coordinates transfer of second transaction information between the second processor bus and each of the first I/O bus or the second I/O bus or the third I/O bus; and wherein the second system module inc