Patents by Inventor Don C. Soltis, Jr.

Don C. Soltis, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clock signal modulation for processors
    Patent number: 10782729
    Abstract: In an embodiment, a processor for clock signal modulation includes a clock source to generate a global clock signal, at least one processor component, a counter, and a circuit. The circuit is to: adjust the counter based on a level of activity of the at least one processor component; modulate, based on a value of the counter, the global clock signal to generate a modulated clock signal; and provide the modulated clock signal to the at least one processor component. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: September 22, 2020
    Assignee: intel Corporation
    Inventors: Bahaa Fahim, Vedaraman Geetha, Don C. Soltis, Jr., Samuel Strom, Jason Crop
  • Mechanism to provide workload and configuration-aware deterministic performance for microprocessors
    Patent number: 10345884
    Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Ankush Varma, Krishnakanth V. Sistla, Martin T. Rowland, Chris Poirier, Eric J. Dehaemer, Avinash N. Ananthakrishnan, Jeremy J. Shrall, Xiuting C. Man, Stephen H. Gunther, Krishna K. Rangan, Devadatta V. Bodas, Don C. Soltis, Jr., Hang T. Nguyen, Cyprian W. Woo, Thi Dang
  • Clock Signal Modulation for Processors
    Publication number: 20190163229
    Abstract: In an embodiment, a processor for clock signal modulation includes a clock source to generate a global clock signal, at least one processor component, a counter, and a circuit. The circuit is to: adjust the counter based on a level of activity of the at least one processor component; modulate, based on a value of the counter, the global clock signal to generate a modulated clock signal; and provide the modulated clock signal to the at least one processor component. Other embodiments are described and claimed.
    Type: Application
    Filed: November 30, 2017
    Publication date: May 30, 2019
    Inventors: Bahaa Fahim, Vedaraman Geetha, Don C. Soltis, JR., Samuel Strom, Jason Crop
  • Systems and methods of sharing processing resources in a multi-threading environment
    Patent number: 7856636
    Abstract: Systems and methods of sharing processing resources in a multi-threading environment are disclosed. An exemplary method may include allocating a lock value for a resource lock, the lock value corresponding to a state of the resource lock. A first thread may yield at least a portion of the processing resources for another thread. The resource lock may be acquired for the first thread if the lock value indicates the resource lock is available.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: December 21, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Rohit Bhatia, Don C. Soltis, Jr.
  • METHOD AND SYSTEM FOR PARALLEL EXECUTION OF MEMORY INSTRUCTIONS IN AN IN-ORDER PROCESSOR
    Publication number: 20100077145
    Abstract: A method of parallel execution of a first and a second instruction in an in-order processor. Embodiments of the invention enable parallel execution of memory instructions that are stalled by cache memory misses. The in-order processor processes cache memory misses of instructions in parallel by overlapping the first cache memory miss with cache memory misses that occur after the first cache memory miss. Memory-level parallelism in the in-order processor can be increased when more parallel and outstanding cache memory misses are generated.
    Type: Application
    Filed: September 25, 2008
    Publication date: March 25, 2010
    Inventors: Sebastian C. Winkel, Kalyan Muthukumar, Don C. Soltis, JR.
  • Error recovery systems and methods for execution data paths
    Patent number: 7447941
    Abstract: Systems and methods for error recovery in an integer execution unit of a multi-core processor are disclosed. In an exemplary embodiment a method may comprise checking parity for a transaction in an execution data path having parallel data registers. The method may also comprise copying one of the parallel data registers to a corrupt data register if parity fails.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: November 4, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Samuel D. Naffziger, Don C. Soltis, Jr.