Patents by Inventor Don Draper
Don Draper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11916076Abstract: The present disclosure provides chip architectures for FPGAs and other routing implementations that provide for increased memory with high bandwidth, in a reduced size, accessible with reduced latency. Such architectures include a first layer in advanced node and a second layer in legacy node. The first layer includes an active die, active circuitry, and a configurable memory, and the second layer includes a passive die with wiring. The second layer is bonded to the first layer such that the wiring of the second layer interconnects with the active circuitry of the first layer and extends an amount of wiring possible in the first layer.Type: GrantFiled: June 29, 2020Date of Patent: February 27, 2024Assignee: Adeia Semiconductor Inc.Inventors: Javier A. Delacruz, Don Draper, Jung Ko, Steven L. Teig
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Patent number: 11894345Abstract: It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.Type: GrantFiled: November 23, 2022Date of Patent: February 6, 2024Assignee: Adeia Semiconductor Inc.Inventors: Javier A DeLaCruz, Don Draper, Belgacem Haba, Ilyas Mohammed
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Publication number: 20230090121Abstract: It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.Type: ApplicationFiled: November 23, 2022Publication date: March 23, 2023Inventors: Javier A. DeLaCruz, Don Draper, Belgacem Haba, Ilyas Mohammed
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Patent number: 11515291Abstract: It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.Type: GrantFiled: April 29, 2019Date of Patent: November 29, 2022Assignee: Adeia Semiconductor Inc.Inventors: Javier A. Delacruz, Don Draper, Belgacem Haba, Ilyas Mohammed
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Publication number: 20200403006Abstract: The present disclosure provides chip architectures for FPGAs and other routing implementations that provide for increased memory with high bandwidth, in a reduced size, accessible with reduced latency. Such architectures include a first layer in advanced node and a second layer in legacy node. The first layer includes an active die, active circuitry, and a configurable memory, and the second layer includes a passive die with wiring. The second layer is bonded to the first layer such that the wiring of the second layer interconnects with the active circuitry of the first layer and extends an amount of wiring possible in the first layer.Type: ApplicationFiled: June 29, 2020Publication date: December 24, 2020Inventors: Javier A. Delacruz, Don Draper, Jung Ko, Steven L. Teig
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Patent number: 10700094Abstract: The present disclosure provides chip architectures for FPGAs and other routing implementations that provide for increased memory with high bandwidth, in a reduced size, accessible with reduced latency. Such architectures include a first layer in advanced node and a second layer in legacy node. The first layer includes an active die, active circuitry, and a configurable memory, and the second layer includes a passive die with wiring. The second layer is bonded to the first layer such that the wiring of the second layer interconnects with the active circuitry of the first layer and extends an amount of wiring possible in the first layer.Type: GrantFiled: October 10, 2018Date of Patent: June 30, 2020Assignee: Xcelsis CorporationInventors: Javier A. Delacruz, Don Draper, Jung Ko, Steven L. Teig
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Publication number: 20200075553Abstract: It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.Type: ApplicationFiled: April 29, 2019Publication date: March 5, 2020Applicant: Xcelsis CorporationInventors: Javier A. DELACRUZ, Don DRAPER, Belgacem HABA, Ilyas MOHAMMED
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Publication number: 20200051999Abstract: The present disclosure provides chip architectures for FPGAs and other routing implementations that provide for increased memory with high bandwidth, in a reduced size, accessible with reduced latency. Such architectures include a first layer in advanced node and a second layer in legacy node. The first layer includes an active die, active circuitry, and a configurable memory, and the second layer includes a passive die with wiring. The second layer is bonded to the first layer such that the wiring of the second layer interconnects with the active circuitry of the first layer and extends an amount of wiring possible in the first layer.Type: ApplicationFiled: October 10, 2018Publication date: February 13, 2020Inventors: Javier A. Delacruz, Don Draper, Jung Ko, Steven L. Teig
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Patent number: 9632883Abstract: An apparatus and method for encoding data are disclosed that may allow for different encoding levels of transmitted data. The apparatus may include an encoder unit and a plurality of transceiver units. The encoder unit may be configured to receive a plurality of data words, where each data word includes N data bits, wherein N is a positive integer greater than one, and encode a first data word of the plurality of data words. The encoded first data word may include M data bits, where M is a positive integer greater than N. Each transceiver unit may transmit a respective data bit of the encoded first data word. The encoder unit may be further configured to receive information indicative of a quality of transmission of the encoded first data word, and encode a second data word of the plurality of data words dependent upon the quality.Type: GrantFiled: December 8, 2014Date of Patent: April 25, 2017Assignee: Oracle International CorporationInventors: Robert P. Masleid, Don Draper, Venkat Krishnaswamy, Paul Loewenstein
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Patent number: 9406364Abstract: Embodiments of an apparatus and method for encoding data are disclosed that may allow for reduced simultaneous switching output noise. The apparatus may include a row decode circuit, a column decode circuit, and a memory array. The row decode circuit and column decode circuits may be configured to decode a first portion and a second portion, respectively, of a given data word of a first plurality of data words, where each data word may include N data bits, and where N is an integer greater than one. The memory array may be configured to store a second plurality of data words where each data word may include M data bits, and where M is an integer greater than N. The memory array may be further configured to retrieve a given data word of the second plurality of data words dependent upon the decoded first and second portions.Type: GrantFiled: June 20, 2014Date of Patent: August 2, 2016Assignee: Oracle International CorporationInventors: Robert P. Masleid, Don Draper, Venkat Krishnaswamy, Paul Loewenstein
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Publication number: 20160164539Abstract: An apparatus and method for encoding data are disclosed that may allow for different encoding levels of transmitted data. The apparatus may include an encoder unit and a plurality of transceiver units. The encoder unit may be configured to receive a plurality of data words, where each data word includes N data bits, wherein N is a positive integer greater than one, and encode a first data word of the plurality of data words. The encoded first data word may include M data bits, where M is a positive integer greater than N. Each transceiver unit may transmit a respective data bit of the encoded first data word. The encoder unit may be further configured to receive information indicative of a quality of transmission of the encoded first data word, and encode a second data word of the plurality of data words dependent upon the quality.Type: ApplicationFiled: December 8, 2014Publication date: June 9, 2016Inventors: Robert P. Masleid, Don Draper, Venkat Krishnaswamy, Paul Loewenstein
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Publication number: 20150371693Abstract: Embodiments of an apparatus and method for encoding data are disclosed that may allow for reduced simultaneous switching output noise. The apparatus may include a row decode circuit, a column decode circuit, and a memory array. The row decode circuit and column decode circuits may be configured to decode a first portion and a second portion, respectively, of a given data word of a first plurality of data words, where each data word may include N data bits, and where N is an integer greater than one. The memory array may be configured to store a second plurality of data words where each data word may include M data bits, and where M is an integer greater than N. The memory array may be further configured to retrieve a given data word of the second plurality of data words dependent upon the decoded first and second portions.Type: ApplicationFiled: June 20, 2014Publication date: December 24, 2015Inventors: Robert P. Masleid, Don Draper, Venkat Krishnaswamy, Paul Loewenstein
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Publication number: 20050257844Abstract: A hydraulic accumulator of the liquid-gas type, comprising a housing (11) defining a chamber (11C), a gas port (30) and a liquid port (19). A gas charging valve (31) is disposed in the gas port (30) to control admission of high pressure gas. A semi-permeable separator (35) is disposed within the housing (11) to separate the internal chamber (11C) into a gas chamber (33) in communication with the gas port (30), and a liquid chamber (21) in communication with the liquid port. A means (41) is within the liquid chamber for collecting gas which passes from the gas chamber (33), through the semi-permeable separator, and into the liquid chamber. Included is a conduit (45) having one end (45a) in communication with the gas collecting means (41), and another end (45b) operably associated with the housing (11, 27) to communicate gas from the collecting means (41) out of the liquid chamber.Type: ApplicationFiled: April 8, 2005Publication date: November 24, 2005Inventor: Don Draper
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Patent number: 6051473Abstract: A process in accordance with the invention enables the manufacturability of raised source-drain MOSFETs. In accordance with the invention, a raised source-drain material, having a window therein, is formed over the substrate. A gate oxide and window sidewall oxides are subsequently formed. Dopants are diffused into the substrate. A gate is formed within the window.Type: GrantFiled: November 22, 1996Date of Patent: April 18, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Emi Ishida, Scott Luning, Dong-Hyuk Ju, Don Draper