Patents by Inventor Don J. Hunter

Don J. Hunter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11703544
    Abstract: Current sensing devices that are capable of surviving harsh ambient environment of ocean worlds, such as Jupiter and Saturn moons are disclosed. The described devices can meet 300 Krad radiation requirements and can survive at cold temperatures down to ?184° C. Exemplary implementations of the constituent circuits of the devices are presented. A scheduling algorithm to perform various measurement by the disclosed current sensing devices is also described.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: July 18, 2023
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Gary S. Bolotin, Don J. Hunter, Malcolm L. Lias, Ben Cheng, John J. Waters, Sunant Katanyoutanant
  • Publication number: 20210389377
    Abstract: Current sensing devices that are capable of surviving harsh ambient environment of ocean worlds, such as Jupiter and Saturn moons are disclosed. The described devices can meet 300 Krad radiation requirements and can survive at cold temperatures down to ?184° C. Exemplary implementations of the constituent circuits of the devices are presented. A scheduling algorithm to perform various measurement by the disclosed current sensing devices is also described.
    Type: Application
    Filed: June 4, 2021
    Publication date: December 16, 2021
    Inventors: Gary S. Bolotin, Don J. Hunter, Malcolm L. Lias, Ben Cheng, John J. Waters, Sunant Katanyoutanant
  • Patent number: 10715142
    Abstract: An LVDS device wherein driver and receiver functionalities are integrated in the same package, signals are routed from the individual driver and receiver elements inside the package such that all inputs are one side of the package, and all outputs are on the opposite side of the package, allowing for an optimized signal flow through the package. All required capacitors and resistors are integrated inside the package; no external electronic components are required. All of the above novelties also contribute to a 6:1 reduction in size compared to current state-of-the-art, for the same number of communication channels. Embodiments include a packaging topology adaptable to extreme environments, including radiation tolerant to 300 kRad (based on the die technology), so that module operational temperature is in a range of ?55° C. to +100° C. and storage temperature can be as low as ?184° C.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: July 14, 2020
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Don J. Hunter, Matthew E. King, Colin McKinney
  • Publication number: 20190165784
    Abstract: An LVDS device wherein driver and receiver functionalities are integrated in the same package, signals are routed from the individual driver and receiver elements inside the package such that all inputs are one side of the package, and all outputs are on the opposite side of the package, allowing for an optimized signal flow through the package. All required capacitors and resistors are integrated inside the package; no external electronic components are required. All of the above novelties also contribute to a 6:1 reduction in size compared to current state-of-the-art, for the same number of communication channels. Embodiments include a packaging topology adaptable to extreme environments, including radiation tolerant to 300 kRad (based on the die technology), so that module operational temperature is in a range of ?55° C. to +100° C. and storage temperature can be as low as ?184° C.
    Type: Application
    Filed: November 7, 2018
    Publication date: May 30, 2019
    Applicant: California Institute of Technology
    Inventors: Don J. Hunter, Matthew E. King, Colin McKinney
  • Patent number: 6201698
    Abstract: A modular electronics packaging system includes multiple packaging slices that are mounted horizontally to a base structure. The slices interlock to provide added structural support. Each packaging slice includes a rigid and thermally conductive housing having four side walls that together form a cavity to house an electronic circuit. The chamber is enclosed on one end by an end wall, or web, that isolates the electronic circuit from a circuit in an adjacent packaging slice. The web also provides a thermal path between the electronic circuit and the base structure. Each slice also includes a mounting bracket that connects the packaging slice to the base structure. Four guide pins protrude from the slice into four corresponding receptacles in an adjacent slice. A locking element, such as a set screw, protrudes into each receptacle and interlocks with the corresponding guide pin. A conduit is formed in the slice to allow electrical connection to the electronic circuit.
    Type: Grant
    Filed: March 9, 1999
    Date of Patent: March 13, 2001
    Assignee: California Institute of Technology
    Inventor: Don J. Hunter