Abstract: A multiple slope integrating analog-to-digital converter (ADC) includes many improvements and refinements which eliminate timing and non-linearity errors which accumulate due to a large number of switching operations that occur over an integrate cycle. The ADC includes an integrator and a comparator in which an input voltage to be measured is applied to a summing node at the input of the integrator during an integrate cycle, while at the same time positive and negative reference currents are selectively applied to the summing node by a controller which monitors the output of the comparator in order to limit the voltage magnitude at the output of the integrator. Thereafter, during a de-integrate cycle, the input voltage is disconnected while progressively shallower ramps are measured with a high-speed clock for greater resolution and accuracy. The comparator has a slight hysteresis built in to slightly separate the switching thresholds for positive-going and negative going ramps.

Abstract: For circuitry having analog and digital circuit sections and a signal flow path therebetween, a guard crossing for establishing electrical isolation and virtually no capacitive coupling between the two sections comprises optical fiber cables extending between circuit boards or between partitioned regions of a common circuit board carrying the analog and digital section for interfacing signals therebetween. Electrooptical transmitters and receivers in each section are coupled to the optical fiber cables. In accordance with one embodiment, bit serial signals are transmitted between the analog and digital sections through a single optical fiber cable for each direction. In another embodiment, a plurality of optical fiber cables for each direction carry the parallel bits of bit parallel signals between the two sections.