Abstract: The harvesting Resistor consists of single or dual supply DC to DC converter, which has a current sense resistor in series with its output port. The sensed current magnitude is coupled back to modulate the duty cycle in a way such that a voltage to current together with the power absorbing relationship of a resistor is appearing at the DC to DC converter's output port. Such an emulated resistor, when connected to an external power source, can efficiently transfer the absorbed energy from an external power source to the single or dual supplies of the DC to DC converter.

Abstract: A split supply DC to DC converter is coupled through a low resistance path to a secondary coil of an ac line transformer, and is used as a high efficiency bidirectional AC to DC convertor. A small sense resistor is placed in series with the secondary in order to measure secondary current. The duty cycle of the DC to DC converter, which defines the voltage of what is normally treated as an output node, is modulated by the monitored secondary current. By coupling such an output node across the secondary coil, a voltage to current relationship is defined across the secondary to be that of a simulated resistor. Such a resistor will absorb power from the AC line and transfer it efficiently to the split supplies. The power transfer direction is reversed with the same efficiency by defining the current to voltage relationship to be one of a negative resistor.

Abstract: The Auto-Aligning Joint Architecture consists of adding endpoint margin regions to sheets which are intended to be joined together. A series of T shaped cuts are made into the margin regions to create alternating connected or disconnected margin regions. The connected margin regions of one sheet align to the disconnected margin regions of the other sheet, such that connected margin regions can fit into disconnected margin regions, thereby joining both sheets together with great precision.

Abstract: A split supply DC to DC converter is coupled through a low resistance path to a secondary coil of an ac line transformer, and is used as a high efficiency bidirectional AC to DC convertor. A small sense resistor is placed in series with the secondary in order to measure secondary current. The duty cycle of the DC to DC converter, which defines the voltage of what is normally treated as an output node, is modulated by the monitored secondary current. By coupling such an output node across the secondary coil, a voltage to current relationship is defined across the secondary to be that of a simulated resistor. Such a resistor will absorb power from the AC line and transfer it efficiently to the split supplies. The power transfer direction is reversed with the same efficiency by defining the current to voltage relationship to be one of a negative resistor.

Abstract: The harvesting Resistor consists of single or dual supply DC to DC converter, which has a current sense resistor in series with its output port. The sensed current magnitude is coupled back to modulate the duty cycle in a way such that a voltage to current together with the power absorbing relationship of a resistor is appearing at the DC to DC converter's output port. Such an emulated resistor, when connected to an external power source, can efficiently transfer the absorbed energy from an external power source to the single or dual supplies of the DC to DC converter.

Abstract: A Folding Comparator circuit which receives an analog input current and both compares it to a DC reference current while at the same time folding the input current around the reference current to be passed on as an output current which can then be passed on to another folding comparator stage. A series of such stages connected together with some XOR logic gates can perform an analog to digital conversion process as a pipeline of auto-folding stages which will instantly convert analog signal to digital signal.

Abstract: Operational transconductance amplifiers have a natural signal capacity format in which signal performance can be expressed in terms of fixed percentages. Input signal can be applied to Operational transconductance amplifiers in this natural signal capacity format in order to optimize performance. A signal which drives a given Operational transconductance amplifier architecture to produce an output current which is at 50% of it's maximum available output current can be thought of as applying an input voltage which is at 50% of an Operational transconductance amplifier's maximum input voltage capacity. In this input/output channel capacity format, dc offset, distortion, and noise all are temperature independent.

Abstract: Operational transconductance amplifiers have a natural signal capacity format in which signal performance can be expressed in terms of fixed percentages. Input signal can be applied to Operational transconductance amplifiers in this natural signal capacity format in order to optimize performance. A signal which drives a given Operational transconductance amplifier architecture to produce an output current which is at 50% of it's maximum available output current can be thought of as applying an input voltage which is at 50% of an Operational transconductance amplifier's maximum input voltage capacity. In this input/output channel capacity format, dc offset, distortion, and noise all are temperature independent.

Abstract: A linearized bipolar differential input stage that contains two high gain current mirrors coupled in series with the input voltage signal through the input transistors to allow the output differential current to greatly exceed the DC output current in a Class AB fashion. The extended output current range over and above the DC current significantly lowers the percentage of effects for both DC offset and noise in the output signal path. Non-linearity cancellation is also optimized for the lowest level of input distortion through adjusting transistor area ratios.

Abstract: A linearized bipolar differential input stage that contains two high gain current mirrors coupled in series with the input voltage signal through the input transistors to allow the output differential current to greatly exceed the DC output current in a Class AB fashion. The extended output current range over and above the DC current significantly lowers the percentage of effects for both DC offset and noise in the output signal path. Non-linearity cancellation is also optimized for the lowest level of input distortion through adjusting transistor area ratios.

Abstract: An improved chopper stabilized operational amplifier is disclosed, along with an improved method of timing the switchings of chopper switches in such an amplifier. The disclosure includes an integrated circuit and method for generating a true random voltage signal having a truly random RMS voltage value within a selected range. The true random voltage signal is obtained by amplifying and bandpass filtering random white noise voltages generated by a component of the circuit. The white noise voltages include shot noise voltages generated by bipolar transistors in an input amplifier stage. The random signal generator circuit and method is employed with an oscillator to form a random clock signal generator on the integrated circuit chip. The amount of time between each clocking pulse output by the random clock signal generator truly randomly varies within a selected range of time, and repeats only by random chance.

Abstract: A chopper stabilized operational amplifier implemented on a single integrated circuit chip is disclosed. The disclosure includes a symmetrical random signal generator circuit that produces a true random voltage signal upon application of a DC bias current. The true random voltage signal is obtained by amplifying and bandpass filtering random white noise voltages generated by a component on the chip. The random signal generator circuit is employed with a symmetrical oscillator to form a random clock signal generator on the same chip. The amount of time between each clocking pulse output by the random clock signal generator randomly varies within a selected range of time. The random clock signal generator is used to control the amount of time between each switching of a chopper switch in the chopper-stabilized operational amplifier, so that the chopping frequency is truly random.

Abstract: To minimize noise generation a chopper switch for a chopper stabilized operational amplifier includes a balanced bridge circuit with two pairs of high-side and low-side transistors connected in parallel. The transistors are not turned completely off but operate in the manner of variable resistors between a high-resistance level and a low-resistance level. One or more additional transistors are include to provide a parasitic capacitance in the break-before-make interval when all of the other transistors are turned off. To provide rail-to-rail operation, complementary circuits contain N-channel and P-channel transistors are connected in parallel between the input and output terminals of the chopper switch.

Abstract: An improved chopper stabilized operational amplifier is disclosed, along with an improved method of timing the switchings of chopper switches in such an amplifier. The disclosure includes an integrated circuit and method for generating a true random voltage signal having a truly random RMS voltage value within a selected range. The true random voltage signal is obtained by amplifying and bandpass filtering random white noise voltages generated by a component of the circuit. The white noise voltages include shot noise voltages generated by bipolar transistors in an input amplifier stage. The random signal generator circuit and method is employed with an oscillator to form a random clock signal generator on the integrated circuit chip. The amount of time between each clocking pulse output by the random clock signal generator truly randomly varies within a selected range of time, and repeats only by random chance.

Abstract: A composite amplifier is constructed by connecting the respective input terminals of a high-frequency amplifier and a precision amplifier together and by connecting the output of the precision amplifier to the offset trim port of the high-frequency amplifier. The amplifiers are structured such than a pole in the frequency response curve of the high-frequency amplifier cancels a zero in the frequency response curve of the precision amplifier, thereby producing a single pole roll off response curve for the composite amplifier. In the preferred embodiment the high-frequency and precision amplifiers are formed on a single chip and the pole-zero match is therefore maintained at all conditions of temperature and other variables.

Abstract: An output stage of a CMOS comparator is designed to have a limited short circuit current, while maintaining maximum output voltage swing and a low quiescent current. The output stage includes a reference voltage generation circuit, which generates a gate voltage at the output transistor of limited range, so that the short circuit current of the output transistor is limited. In one embodiment, the reference voltage is generated by a plurality of serially connected diodes.