Abstract: The disclosure provides event-controlled operations for an internal hardware/softward monitor for a processor in a data processing system. It embeds and distributes in each processor at least one instrumentation table unit (ITU) and event detection circuitry to detect events and conditions for collecting event-sampled hardware signals provided in the processor hardware in which the respective ITU is embedded. Instrumentation measurement is controlled centrally in the system. Sampling of the CPU signals for recording in the ITU is done at (or a sub-multiple of) the occurrence rate of the selected event(s) in the processor. The sampled signals are recorded in the ITU. The ITUs of plural processors are asynchronously operated in a system. The event-driven monitoring circuitry may be solely provided in an ITU, or it may be superimposed on a timer-driven internal instrumentation system of the type described in U.S. Pat. No. 4,590,550 in which the ITU is shared between event and timer driven modes of operation.

Abstract: The embodiment provides an independent data bus path between a random access page storage (PS), and a main storage (MS), wherein this independent data bus does not pass through any channel processor (CH) or central processor (CP). Page data transfers on the independent data bus can be controlled either (1) asynchronously by a channel processor (independently of any central processor instruction stream), or (2) synchronously by a CP (independently of any CH operation). Novel CP instructions enable the CP to synchronously control the transfer of pages in either direction on the independent data bus.A channel program for controlling the page transfer may be initiated by a start I/O (SIO) or start subchannel (SSCH) instruction in the CPU, and it accesses a special field in a channel address word (CAW) that designates the use of the page storage. Novel PS channel command words (CCWs) in the channel program enable CH to control page transfers on the independent data bus.