Abstract: A heat exchanger including a primary tube including a first flat plate and a first shaped plate connected to each other to form a first fluid channel. The first flat plate and the first shaped plate include fluid openings to enable fluid flow to and from the primary tube.

Abstract: An attachment for a heat exchange plate, having an attachment base plate extending within a base plane, having a bottom side and a top side between which a thickness of the attachment base plate extends, with a plurality of contact portions extending away from the top side independently from each other. The attachment base plate is of rectangular, elongated outline extending along an attachment longitudinal axis and an attachment lateral axis, the extension along the attachment longitudinal axis being predominant. At least one contact portion has a different longitudinal length than another contact portion, the longitudinal length being measured along the attachment longitudinal axis.

Abstract: A heat exchanger assembly, including a heat exchanger with a primary tube including a first fluid channel for a heat exchange fluid; a first heat source module with a plurality of first heat sources; an attachment with a plurality of contact portions exposed to the plurality of first heat sources, mounted on the primary tube adjacent to the first fluid channel.

Abstract: An integrated circuit device having a test sequence generator, first and second transceivers and a test sequence analyzer. The test sequence generator generates a test data sequence in response to a test mode selection. The first transceiver receives the test data sequence from the test sequence generator and is configured in a loopback mode to transmit and receive the test data sequence. The second transceiver receives the test data sequence received by the first transceiver and is configured in a loopback mode to transmit and receive the test data sequence. The test sequence analyzer determines whether the test data sequence received by the second transceiver matches the test data sequence generated by the test sequence generator.

Abstract: An integrated circuit device having a test sequence generator, first and second transceivers and a test sequence analyzer. The test sequence generator generates a test data sequence in response to a test mode selection. The first transceiver receives the test data sequence from the test sequence generator and is configured in a loopback mode to transmit and receive the test data sequence. The second transceiver receives the test data sequence received by the first transceiver and is configured in a loopback mode to transmit and receive the test data sequence. The test sequence analyzer determines whether the test data sequence received by the second transceiver matches the test data sequence generated by the test sequence generator.

Abstract: An integrated capacitor includes a device region of first conductivity type in a semiconductor substrate, a source/drain region of the first conductivity type in the device region with a higher doping concentration than the device region, a gate insulator over the device region, and a gate over the gate insulator. A first terminal is coupled to the source/drain region, and a second terminal is coupled to the gate. Advantageously, the integrated capacitor is operated with the device region beneath the gate driven into accumulation instead of inversion. This allows a lower voltage to be applied to the gate, which allows for a thinner gate insulator to be used resulting in higher capacitance per unit area. Furthermore, since the device region is much thicker and more highly conductive than an inversion layer, the integrated capacitor has greatly improved frequency response.

Abstract: An active power supply filter effectively eliminates power supply noise using a resistive element and a capacitive element coupled at a node, and a switch with a control terminal controlled by the node. The active power supply filter is suitable for high frequency operation of a voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) of a high-speed microprocessor. The active power supply filter removes VCO noise that would otherwise create jitter that reduces the effective clock cycle of the microprocessor. The active power supply filter is similarly useful in applications other than VCOs, PLLs, and microprocessors in which removal of substantial amounts of noise from the power supply is useful.

Abstract: A method of making an IGFET with a selected threshold voltage is disclosed. The method includes providing a semiconductor substrate with a device region that includes a source region, a drain region and a channel region therebetween, forming a gate over the channel region, introducing a threshold adjust dopant into the channel region after forming the gate without transferring essentially any of the threshold adjust dopant through the gate, thereby adjusting a threshold voltage of the IGFET, and forming a source in the source region and a drain in the drain region. Preferably, the threshold adjust dopant is introduced by implanting the threshold adjust dopant into the source region and diffusing the threshold adjust dopant from the source region into the channel region before providing any source/drain doping.

Abstract: A high-performance dynamic flip-flop circuit implementation. The dynamic flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (319). The flip-flop comprises a delay block (317) coupled to a clock input (305). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (440) of the delayed clock output (319) follows a rising edge (444) of a clock signal after a delay period (448). The flip-flop clocks in new data at a data input (305) in response to the clock input (310) during this delay period (448). Data is held in a storage block (360). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.

Abstract: Generally, decreasing the length of the channel in a CMOS transistor increases the speed of the transistor. However, the degree that the channel can be minimized is limited due to Hot Carrier Injection ("HCI"), which is related to the drain to source voltage and channel length. The present invention increases the speed of a circuit by decreasing the channel length of subset of transistors in the circuit. The subset is chosen by identifying instances where more than one transistor in series is used to discharge a capacitance. Those transistors are subject to lower drain to source voltages; therefore, the channel length can be reduced without suffering from the effects of HCI.

Abstract: An active power supply filter effectively eliminates power supply noise using a resistive element and a capacitive element coupled at a node, and a switch with a control terminal controlled by the node. The active power supply filter is suitable for high frequency operation of a voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) of a high-speed microprocessor. The active power supply filter removes VCO noise that would otherwise create jitter that reduces the effective clock cycle of the microprocessor. The active power supply filter is similarly useful in applications other than VCOs, PLLs, and microprocessors in which removal of substantial amounts of noise from the power supply is useful.

Abstract: A high-performance flip-flop circuit implementation. The flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (407). The flip-flop comprises a delay block (405) coupled to a clock input (210). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (540) of the delayed clock output (407) follows a rising edge (544) of a clock signal after a delay period (548). The flip-flop clocks in new data at a data input (205) in response to the clock input (210) during this delay period (548). Data is held in a storage block (450). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.

Abstract: The present invention discloses a differential logic circuit and sensing method providing differential sensing with greater speed and higher density than prior art techniques. One or more input signals are provided to a logic array and two output signals are produced from the logic array wherein one output signal of the logic array is a bit-line and one output signal of the logic array is a bit-bar-line as a reference signal, wherein both signals are provided as input signals to a differential sense amplifier having a binary output signal. The bit-line and the bit-bar-line are precharged to the same voltage level and a controlled input source-grounded transistor having less than fill drive strength is coupled to the bit-bar-line. A source-grounded transistor is coupled to each input signal of the logic array and is programmable to the bit-line by coupling the drain of the source-grounded transistor to the bit-line.

Abstract: Generally, decreasing the length of the channel in a CMOS transistor increases the speed of the transistor. However, the degree that the channel can be minimized is limited due to Hot Carrier Injection ("HCI"), which is related to the drain to source voltage and channel length. The present invention increases the speed of a circuit by decreasing the channel length of subset of transistors in the circuit. The subset is chosen by identifying instances where more than one transistor in series is used to discharge a capacitance. Those transistors are subject to lower drain to source voltages; therefore, the channel length can be reduced without suffering from the effects of HCI.

Abstract: A semiconductor memory array with Built-in Self-Repair (BISR) includes redundancy circuits associated with failed row address stores to drive redundant row word lines, thereby obviating the supply and normal decoding of a substitute addresses. NOT comparator logic compares a failed row address generated and stored by BISR circuits to a row address supplied to the memory array. A TRUE comparator configured in parallel with the NOT comparator simultaneously compares defective row address signal to the supplied row address. Since NOT comparison is performed quickly in dynamic logic without setup and hold time constraints, timing impact on a normal (non-redundant) row decode path is negligible, and since TRUE comparison, though potentially slower than NOT comparison, itself identifies a redundant row address and therefore need not employ an N-bit address to selected word-line decode, redundant row addressing is rapid and does not adversely degrade performance of a self-repaired semiconductor memory array.

Abstract: A high-performance flip-flop circuit implementation. The flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (407). The flip-flop comprises a delay block (405) coupled to a clock input (210). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (540) of the delayed clock output (407) follows a rising edge (544) of a clock signal after a delay period (548). The flip-flop clocks in new data at a data input (205) in response to the clock input (210) during this delay period (548). Data is held in a storage block (450). The flip-flop has extremely good transient characteristics, especially setup and clock-to-output times. The flip-flop consumes no static power.

Abstract: A high-performance dynamic flip-flop circuit implementation. The dynamic flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (319). The flip-flop comprises a delay block (317) coupled to a clock input (305). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (440) of the delayed clock output (319) follows a rising edge (444) of a clock signal after a delay period (448). The flip-flop clocks in new data at a data input (305) in response to the clock input (310) during this delay period (448). Data is held in a storage block (360). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.

Abstract: A first transistor is connected to a second transistor so that the first and second transistors may be initially biased in a non-conducting state when a first node is at a first voltage potential and a second node is at a second voltage potential. A potential altering circuit selectively alters the voltage potential at the first and second nodes, causes the first and second transistors to be in a conducting state for accelerating a voltage transistion at the first and second nodes toward final values, and maintains the first and second nodes at their final voltage potentials for implementing a desired Boolean function.

Abstract: A carry indicating circuit selectively generates a carry-in signal indicating whether the addition of a first plurality of bits results in a carry. A first carry chain circuit selectively generates a first carry-out signal indicating whether the addition of a second plurality of bits together with a carry from the addition of the first plurality of bits results in a carry, and a second carry chain circuit selectively generates a second carry-out signal indicating whether the addition of the second plurality of bits without a carry from the addition of the first plurality of bits results in a carry. Selection circuitry, coupled to the carry indicating circuit and to the first and second carry chain circuits, selects either the first carry-out signal or the second carry-out signal in response to the carry-in signal.

Abstract: A first transistor is connected to a second transistor so that the first and second transistors may be initially biased in a non-conducting state when a first node is at a first voltage potential and a second node is at a second voltage potential. A potential altering circuit selectively alters the voltage potential at the first and second nodes, causes the first and second transistors to be in a conducting state for accelerating a voltage transistion at the first and second nodes toward final values, and maintains the first and second nodes at their final voltage potentials for implementing a desired Boolean function. The biasing circuit is connected to facilitate turning off the first and second transistors when the circuit is being reset for subsequent Boolean evaluations. More specifically, the biasing circuit inhibits current flow through the first and second transistors during a precharge operation to prevent excessive power consumption.