Patents by Inventor Donald B. MacMillen

Donald B. MacMillen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Behavioral synthesis links to logic synthesis
    Patent number: 6505339
    Abstract: A method and an apparatus for coupling the results of behavioral synthesis with those of logic synthesis. It uses a timing verifier to precalculate the timing characteristics of a circuit for use by behavioral synthesis. Timing for control chaining is included in the precalculated timing characteristics. Once behavioral synthesis is complete, logic synthesis is informed of timing constraints introduced by behavioral synthesis.
    Type: Grant
    Filed: January 4, 2000
    Date of Patent: January 7, 2003
    Assignee: Synopsys, Inc.
    Inventors: Ronald A. Miller, Donald B. MacMillen, Tai A. Ly, David W. Knapp
  • Behavioral synthesis links to logic synthesis
    Patent number: 6026219
    Abstract: A method and an apparatus for coupling the results of behavioral synthesis with those of logic synthesis. It uses a timing verifier to precalculate the timing characteristics of a circuit for use by behavioral synthesis. Timing for control chaining is included in the precalculated timing characteristics. Once behavioral synthesis is complete, logic synthesis is informed of timing constraints introduced by behavioral synthesis.
    Type: Grant
    Filed: May 12, 1995
    Date of Patent: February 15, 2000
    Assignee: Synopsys, Inc.
    Inventors: Ronald A. Miller, Donald B. MacMillen, Tai A. Ly, David W. Knapp
  • Methods for automatically pipelining loops
    Patent number: 5764951
    Abstract: A method and an apparatus for creating a representation of a circuit with a pipelined loop from an HDL source code description. It infers a circuit including a pipelined loop which has cycle level simulation behavior matching that of the source HDL. Loop carry dependencies and memory and signal I/O accesses within the loop are scheduled correctly.
    Type: Grant
    Filed: May 12, 1995
    Date of Patent: June 9, 1998
    Assignee: Synopsys, Inc.
    Inventors: Tai A. Ly, David W. Knapp, Ronald A. Miller, Donald B. Macmillen
  • Methods for automatically pipelining loops
    Patent number: RE40925
    Abstract: A method and an apparatus for creating a representation of a circuit with a pipelined loop from an HDL source code description. It infers a circuit including a pipelined loop which has cycle level simulation behavior matching that of the source HDL. Loop carry dependencies and memory and signal I/O accesses within the loop are scheduled correctly.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: September 29, 2009
    Assignee: Synopsys, Inc.
    Inventors: Tai A. Ly, David W. Knapp, Ronald A. Miller, Donald B. Macmillen