Abstract: An adaptive delta modulation system wherein the input analog signal is periodically sampled and a binary bit is generated for each period, the logic level of the binary bit being dependent on whether the sampled signal is greater or smaller than the approximate signal of the previous sample. Decoding apparatus converts the stream of binary bits to approximate the analog signal by periodically charging or discharging a capacitor integrator by predetermined variable steps. The charging or discharging of the integrator during each period is determined by the logic level of the binary bits, whereas the increase or decrease in step size for successive periods is determined by successive similar signal binary bits or successive dissimilar bits, respectively. The increase or decrease in step size is achieved by storing a binary step size number S in a register and adding or subtracting a fraction of the number to or from itself during each period, producing a new step size number for each period.