Abstract: The present invention provides a method of manufacturing an integrated circuit having a capping layer over a thick metal feature. In one embodiment, the method comprises forming first and second oxide layers over the thick metal feature, forming a composite oxide layer including an oxide spacer by etching the first and second oxide layers, and forming a capping layer over the composite oxide layer. More specifically, forming the first oxide layer involves using a high density plasma (HDP) process, forming the second oxide layer involves using a plasma enhanced chemical vapor deposition (PECVD) process, and forming the composite oxide layer preferably involves etching with a reactive ion etch.

Abstract: The present invention provides, for use in an integrated circuit structure having a prior level that includes a foundation dielectric formed over a conductive polycrystalline material, a capacitor comprising first and second electrodes having a capacitor dielectric formed therebetween. The first electrode is formed immediately over the prior level and extends beyond a common area of the first and second electrodes and connects the capacitor to the prior level outside of the common area. The capacitor is free of a direct electrical contact with the prior level; that is, the capacitor is not connected to the prior level by a window or other interconnect structure that extends directly from the capacitor itself within the common area. Electrical connection of the capacitor to the prior level is made outside the common area of the capacitor.