Patents by Inventor Donald E. Hawk
Donald E. Hawk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20160260662Abstract: Systems, methods, devices, circuits for distributing signals and/or potentials on an integrated circuit.Type: ApplicationFiled: March 4, 2015Publication date: September 8, 2016Inventors: Donald E. Hawk, Larry Golick, Bei Qi Wang
-
Patent number: 8736076Abstract: One aspect provides an integrated circuit (IC) packaging assembly that comprises a substrate having conductive traces located thereon, wherein the signal traces are located in an IC device region and the power traces are located in a wafer level fan out (WLFO) region located lateral the IC device region. This embodiment further comprises a first IC device located on a first side of the substrate within the IC device region and that contacts the signal traces in the IC device region. A second IC device is located on a second side of the substrate opposite the first side and overlaps the IC device region and the WLFO region. The second IC device contacts a first portion of the signal traces in the IC device region and contacts a first portion of the power traces in the WLFO region.Type: GrantFiled: August 10, 2012Date of Patent: May 27, 2014Assignee: LSI CorporationInventor: Donald E. Hawk
-
Publication number: 20140131854Abstract: One aspect provides an integrated circuit (IC) multi-chip packaging assembly, comprising a first IC chip having packaging substrate contacts and bridging block contacts, a second IC chip having packaging substrate contacts and bridging block contacts, and a bridging block partially overlapping the first and second IC chips and having interconnected electrical contacts on opposing ends thereof that contact the bridging block contacts of the first IC chip and the second IC chip to thereby electrically connect the first IC chip to the second chip.Type: ApplicationFiled: November 13, 2012Publication date: May 15, 2014Applicant: LSI CorporationInventors: Donald E. Hawk, John W. Osenbach, James C. Parker
-
Publication number: 20140042601Abstract: One aspect provides an integrated circuit (IC) packaging assembly that comprises a substrate having conductive traces located thereon, wherein the signal traces are located in an IC device region and the power traces are located in a wafer level fan out (WLFO) region located lateral the IC device region. This embodiment further comprises a first IC device located on a first side of the substrate within the IC device region and that contacts the signal traces in the IC device region. A second IC device is located on a second side of the substrate opposite the first side and overlaps the IC device region and the WLFO region. The second IC device contacts a first portion of the signal traces in the IC device region and contacts a first portion of the power traces in the WLFO region.Type: ApplicationFiled: August 10, 2012Publication date: February 13, 2014Applicant: LSI CorporationInventor: Donald E. Hawk
-
Patent number: 8627256Abstract: A method of determining signal routing in an integrated circuit includes providing first coordinates of an input/output cell and second coordinates of an input/output pad to a parametric routing module. The parametric routing module receives at least one wire path parameter. The parametric routing module uses the at least one connection path parameter to determine a physical dimension of a wire path between the first coordinates and the second coordinates.Type: GrantFiled: April 25, 2011Date of Patent: January 7, 2014Assignee: LSI CorporationInventor: Donald E. Hawk
-
Publication number: 20130154109Abstract: The disclosure provides an interposer with conductive paths, a three-dimensional integrated circuit (3D IC), a method of reducing capacitance associated with conductive paths in an interposer and a method of manufacturing an interposer. In one embodiment the interposer includes: (1) a semiconductor substrate that is doped with a dopant, (2) conductive paths located within said semiconductor substrate and configured to provide electrical routes therethrough and (3) an ohmic contact region located within said semiconductor substrate and configured to receive a back bias voltage.Type: ApplicationFiled: December 16, 2011Publication date: June 20, 2013Applicant: LSI CorporationInventors: Ramnath Venkatraman, John W. Osenbach, Anwar Ali, Donald E. Hawk, Robert J. Madge
-
Patent number: 8370777Abstract: A method of generating a model of a leadframe IC package, a leadframe modeler and an IC design system are disclosed. In one embodiment the method includes: (1) adding connectivity information to a geometric representation of a leadframe, wherein the connectivity information represents electrical connections between the IC die and leads of the leadframe and (2) formatting the leads to represent BGA point of contacts for the IC die.Type: GrantFiled: June 16, 2009Date of Patent: February 5, 2013Assignee: LSI CorporationInventors: Donald E. Hawk, Jr., Stephen M. King, Jeffrey M. Klemovage, John J. Krantz, Allen S. Lim, Ashley Rebelo, Richard J. Sergi
-
Publication number: 20120272203Abstract: A method of determining signal routing in an integrated circuit includes providing first coordinates of an input/output cell and second coordinates of an input/output pad to a parametric routing module. The parametric routing module receives at least one wire path parameter. The parametric routing module uses the at least one connection path parameter to determine a physical dimension of a wire path between the first coordinates and the second coordinates.Type: ApplicationFiled: April 25, 2011Publication date: October 25, 2012Applicant: LSI CORPORATIONInventor: Donald E. Hawk
-
Publication number: 20100318340Abstract: A method of generating a model of a leadframe IC package, a leadframe modeler and an IC design system are disclosed. In one embodiment the method includes: (1) adding connectivity information to a geometric representation of a leadframe, wherein the connectivity information represents electrical connections between the IC die and leads of the leadframe and (2) formatting the leads to represent BGA point of contacts for the IC die.Type: ApplicationFiled: June 16, 2009Publication date: December 16, 2010Applicant: LSI CorporationInventors: Donald E. Hawk, JR., Stephen M. King, Jeffrey M. Klemovage, John J. Krantz, Allen S. Lim, Ashley Rebelo, Richard J. Sergi
-
Patent number: 7709861Abstract: Various systems and methods for implementing multi-mode semiconductor devices are discussed herein. For example, a multi-mode semiconductor device is disclosed that includes a device package with a number of package pins. In addition, the device includes a semiconductor die or substrate with at least two IO buffers. One of the IO buffers is located a distance from a package pin and another of the IO buffers is located another distance from the package pin. One of the IO buffers includes first bond pad electrically coupled to a circuit implementing a first interface type and a floating bond pad, and the other IO buffer includes a second bond pad electrically coupled to a circuit implementing a second interface type. In some cases, the floating bond pad is electrically coupled to the circuit implementing the second interface type via a conductive interconnect, and the floating bond pad is electrically coupled to the package pin.Type: GrantFiled: March 12, 2007Date of Patent: May 4, 2010Assignee: Agere Systems Inc.Inventors: Parag Madhani, Paul F. Barnes, Donald E. Hawk, Jr., Kandaswamy Prabakaran
-
Publication number: 20080061319Abstract: Various systems and methods for implementing multi-mode semiconductor devices are discussed herein. For example, a multi-mode semiconductor device is disclosed that includes a device package with a number of package pins. In addition, the device includes a semiconductor die or substrate with at least two IO buffers. One of the IO buffers is located a distance from a package pin and another of the IO buffers is located another distance from the package pin. One of the IO buffers includes first bond pad electrically coupled to a circuit implementing a first interface type and a floating bond pad, and the other IO buffer includes a second bond pad electrically coupled to a circuit implementing a second interface type. In some cases, the floating bond pad is electrically coupled to the circuit implementing the second interface type via a conductive interconnect, and the floating bond pad is electrically coupled to the package pin.Type: ApplicationFiled: March 12, 2007Publication date: March 13, 2008Applicant: Agere Systems Inc.Inventors: Parag Madhani, Paul F. Barnes, Donald E. Hawk, Kandaswamy Prabakaran
-
Patent number: 7271485Abstract: Various systems and methods for implementing multi-mode semiconductor devices are discussed herein. For example, a multi-mode semiconductor device is disclosed that includes a device package with a number of package pins. In addition, the device includes a semiconductor die with at least two IO buffers. One of the IO buffers is located a distance from a particular package pin and another of the IO buffers is located a greater distance from the particular package pin. The IO buffer located closest to the package pin includes first bond pad electrically coupled to a circuit implementing a first interface type and a first floating bond pad, and the other IO buffer includes a second bond pad electrically coupled to a circuit implementing a second interface type and a second floating bond pad.Type: GrantFiled: September 11, 2006Date of Patent: September 18, 2007Assignee: Agere Systems Inc.Inventors: Parag N. Madhani, Paul F. Barnes, Donald E. Hawk, Jr., Kandaswamy Prabakaran
-
Patent number: 6476472Abstract: An integrated circuit (IC) package includes an IC having at least one ESD protection circuit that provides protection against electrostatic discharge. The IC has a plurality of bond pads that are not coupled to the ESD protection circuit. The IC is connected to a substrate. The substrate has a first plurality of conductive traces, which are connected to respective bond pads of the IC, and a second plurality of conductive traces, which are not connected to any of the plurality of bond pads of the IC. Either the substrate or the IC has a common conductive trace that is connected to the ESD protection circuit. Each of the second plurality of conductive traces is connected to the common conductive trace.Type: GrantFiled: August 18, 2000Date of Patent: November 5, 2002Assignee: Agere Systems Inc.Inventors: Kerry L. Davison, Donald E. Hawk, Jr., Yehuda Smooha