Abstract: A static random access memory arrangement provides for accessing a desired number of bits (i.e., a byte) simultaneously by placing the accessed columns adjacent one another. For example, if the memory provides 8 bits when accessed, then a group of 8 adjacent columns is addressed, whereas the prior art provided for accessing one column out of each of 8 separate groups. The present scheme provides for improved utilization of spare columns for redundancy purposes, and also allows for partial row selection for reduced power consumption and noise.

Abstract: A spare decoder provides for the substitution of a spare component for repair of a defective semiconductor chip. For example, a spare row or column of memory cells can be substituted for a defective row or column of a memory chip by fusing fusible links in the decoder. The present invention implements the decoder in CMOS technology. To minimize power consumption, means are included for preventing current flow in an unused spare without having to fuse a link.

Abstract: An improved field effect transistor sense amplifier uses a cross-coupled pair of first transistors (Q1, Q2) with separate third and fourth transistors (Q3, Q4) connected by the sources (12, 14) to each of one of cross-coupled terminals (12, 14) of the cross-coupled pair (Q1, Q2). Read circuitry (Q7, Q8) is connected directly to the cross-coupled terminals (12, 14) of the cross-coupled pair (Q1, Q2). Write circuitry (Q9, Q10) is connected to the drains (18, 22) of the third and fourth transistors (Q3, Q4).

Abstract: An MOS dynamic random access memory (RAM) includes an array of memory cells arranged in rows and columns. The array is divided into two or more sub-arrays. In an operating cycle where a cell is being accessed for reading and/or writing, only the sub-array containing the accessed cell is fully selected while the other sub-arrays are partially selected. A fully selected sub-array is one in which both a row and a column are selected, whereas in a partially selected sub-array, only a row is selected. In the partially selected sub-array where only refreshing of the cells in the selected row takes place, the column decoders and drivers remain inactive throughout the memory cycle.

Abstract: An MOS dynamic random access memory (RAM) includes an array of memory cells arranged in rows and columns. The array is divided into two or more sub-arrays. During an operating cycle latching of the sense amplifiers in the sub-arrays is staggered to avoid coincidence of current peaks each arising when the sense amplifiers in one of the sub-arrays are simultaneously latched. Latching takes place first in a sub-array in which a cell is selected. Recovery of the column conductors in the sub-arrays is also staggered to avoid coincidence of current peaks each occurring when one of the sub-arrays is recovered. The sub-array in which a cell is selected is recovered last.