Abstract: A communication protocol processor is presented including a transmit unit and a receive unit, each having multiple microprocessor cores connected in series. Each microprocessor core performs an operation upon a stream of communication data, conducted along a data path, according to instructions and associated data stored within a code memory unit. A change in the operation performed by a given microprocessor core is effectuated during communication protocol processor operation by transmitting new instructions and associated data to the microprocessor core along the data path. The new instructions and data modify the existing instructions and associated data stored within the code memory unit. The transmit unit of the communication protocol processor receives packet (i.e., transmit) data in parallel units and produces a framed serial transmit data stream.

Abstract: The scalable virtual timer system or subsystem implements multiple hardware timers with minimal silicon overhead. In one embodiment, for each virtual timer of a plurality of virtual timers, a content addressable memory stores a sum of an “initial state” of a free running counter and a desired count duration for the virtual timer. When the stored value matches a current state of the free running counter, the content addressable memory generates a terminal count for the virtual timer. In an alternative embodiment, for each virtual timer, a period register of a set of period registers stores a sum of a desired count duration for a virtual timer and an “initial state” of the free running counter. A comparator of a set of comparators generates a terminal count for a virtual timer when a current state of the free running counter matches the sum stored in a period register associated with the virtual timer.

Abstract: An integrated processor is fabricated on a single monolithic circuit and employs circuitry to accommodate data-intensive, view-intensive and voice-intensive requirements of modern-day PIDs. The integrated processor includes a CPU core, a memory controller, and a variety of peripheral devices to achieve versatility and high performance functionality. The integrated processor consumes less power by provision of a clock control unit including a plurality of phase-locked loops for generating clock signals of differing frequencies to appropriately clock the various subsystems of the integrated processor. The clock signals provided to the various subsystems by the clock control unit are derived from a single crystal oscillator input signal. A power management unit is incorporated within the integrated processor to control the frequency and/or application of certain clock signals to the various subsystems, as well as to control other power management related functions.

Abstract: A sense amplifier for a read only memory array which is formed from a multiplicity of NAND organized FET stacks. The sense amplifier compares the current sinking capacity of a selected bit line stack with that of a reference stackline, the difference being detected as a voltage shift in a differential stage. Pass FETs with gate electrodes biased in inverse proportion to the bit and reference line potentials are serially connected between the corresponding lines and reference nodes.

Abstract: A field effect transistor driver circuit figured to have different rates of change of the output signal depending on fabrication mask designation of selected transistors to be either depletion or enhancement type devices.

Abstract: A read-only memory array formed from a multiplicity of NAND-organized FET stacks which are arranged in pairs and connected in alternate succession of adjacent pairs at opposite ends. Selection of stacks by pairs is performed by connecting the common node of four stacks at one end to a bit line and the common node of another four stacks, only two being common with the former four stacks, to ground potential. Selection between adjacent stack pairs is performed by bank select FETs in each stack. Each stack is precharged at both ends prior to selection. A sense amp is utilized to compare the current sinking capacity of the selected bit line with a reference stack, the difference being detected in a differential amplifier. A programmable output driver provides an adjustable rate of change in the output signal for step input signals.

Abstract: A comparator circuit suitably configured and synchronously operated to distinguish between the levels of two input signals and to provide the relative standing of the levels in binary format. In one form, a symmetrically organized circuit having the fundamental structure of a bistable multivibrator is initially operated in a differential mode and subsequently transitioned to a latch mode. Appropriate constant current source biasing shifts the differential mode operation to optimize amplifier element gain characteristics for the levels of input signals received. The amplified difference between the two input signals is stored within various capacitive elements of the circuit output stages. During the differential mode, the bistable multivibrator cross-coupling elements are disabled.

Abstract: A volatile/non-volatile RAM cell employing a bistable multivibrator with non-volatile, alterable-threshold capacitors coupled to the output terminals thereof to provide backup data storage in a power-down situation. In one embodiment, the non-volatile capacitors each have a non-alterable section and an alterable section, the non-alterable section having either a depletion or an enhancement threshold. The V/NV RAM cell employs a pair of field effect transistors of depletion or enhancement type to couple the non-volatile capacitors to the output terminals. These coupling transistors form with the non-volatile capacitors a pair of nodes. The coupling transistors are biased such that a write voltage signal applied to the gates of the non-volatile capacitors produces a bootstrapped voltage on one of the pair of nodes which is effectively isolated from the output terminals of the cell.

Abstract: An FET read-only memory cell capable of storing more than one bit per cell. The channel geometry of the FET cell is selected to provide an electrical output that is characteristic of a predetermined combination of bits. For example, the FET channel width can be selected to provide one of 2.sup.n predetermined output voltage values which correspond to the 2.sup.n possible arrangements of n bits. The read function utilizes 2.sup.n -1 sense amplifiers, which are connected to the FET. Each sense amplifier is selectively activated at a separate one of 2.sup.n -1 voltage levels which is intermediate two adjacent values of the 2.sup.n output voltages. The collective outputs of the sense amplifiers drive a logic circuit for decoding the values of the n data bits represented by the FET channel width.

Abstract: A plasma charge display device having a channel containing an ionizable medium with the channel defining an endless length as in the case of a circular channel. At least one input electrode is located in a first position, and transfer electrodes extend away from the input electrode on opposite sides thereof completely along the length of the channel. Gas ionization results in the formation and shifting of light emitting areas in either direction relative to the position of the input electrode. The transfer electrode positions are related to the input electrode position in a manner such that the light emitting areas can be shifted through the position of the input electrode from one side to the other thereof.