Abstract: The invention is a defect tolerant memory for a computer system. The defect tolerant memory has a main memory, a redundant memory and a mask memory. The redundant memory receives and stores data redundant to that addressed to defective cells in the main memory. The redundant memory has multiple memory levels and uses a randomness technique to store redundant data for all chips of the main memory. The mask memory stores the location of each defect of main memory and indicates when a defective word is addressed in main memory. The mask memory is made up of multiple bit mask memories each cooperating with one of the redundant memory levels. Each bit-mask memory has multiple sub-memory units which use a randomness technique to store the addresses of defects in main memory.