Abstract: A method and circuit (20) for reducing flicker. Pixel values (Y.sub.0, Y.sub.1, Y.sub.-1) are transmitted to input terminals (23, 21, 22) of the circuit (20). A first difference magnitude is calculated by subtracting the pixel value (Y.sub.0) of a middle pixel from the pixel value (Y.sub.-1) of an upper pixel and taking an absolute value of the result. A second pixel magnitude is calculated by subtracting the pixel value (Y.sub.0) of the middle pixel from the pixel value of a lower pixel and taking an absolute value of the result. A larger of the first and second pixel magnitudes is compared to a user-selected threshold value. The pixel value (Y.sub.0) of the middle pixel is either changed or left unchanged in accordance with the results of the comparison.

Abstract: A circuit and method for demodulation of transmitted phase-coherent signals including recovery of the clock and data signals associated therewith. A clock recovery circuit detects a zero crossing of the transmitted signal which occurs every one-half period of the lowest frequency transmitted signal. A data recovery circuit detects the presence or absence of a zero crossing during a window portion of each one-half period of the lowest frequency transmitted signal.

Abstract: A memory chip containing a standard dynamic RAM having the capability to serially read out data at a high rate of speed while performing standard RAM operations is provided. A standard memory latches a complete row of data into a latch. The data from the latch is then transferred upon command to a second latch or shift register where it is shifted out independently of the operation of the RAM.