Abstract: A method and apparatus for efficiently and economically using partially good memory modules to construct a memory unit of predetermined aggregate capacity is described, using a universal wiring pattern on a substrate, including positions thereon with circuitry adapted for connecting to data outputs from a plurality of partially good memory modules, memory unit data output circuitry, and selectively interconnectable--during a final manufacturing step--lines associated with memory module data outputs and with the memory unit data outputs, thereby enabling connection of data outputs from good sections of the partially good memory modules to memory unit data outputs.