Patents by Inventor Donald L. Scharfetter

Donald L. Scharfetter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6100709
    Abstract: A wafer testing rig includes a stand, a first contact component, a second contact component and a biasing device. The first contact component is mounted to the stand. The second contact component is mounted to the stand for movement towards and away from the first contact component. The first and second contact components are shaped so that a wafer, when located between the contact components, is deflected into a dome shape when the second contact component is moved towards the first contact component. The biasing device is operable to move the second contact component towards and away from the first contact component. An electrical tester is provided to test the wafer.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: August 8, 2000
    Assignee: Intel Corporation
    Inventors: Thomas N. Marieb, Krishna Seshan, Donald L. Scharfetter
  • Patent number: 5416729
    Abstract: A topography simulator using a "Generalized Solid Modeling (GSM) method" to simulate isotropic or anisotropic deposition and etch process steps on a workpiece. A solids modeling system that utilizes a boundary representation model for representing material object solids provides a basis for the topography simulator. A workpiece in the model is comprised of a collection of material solids. The present invention provides for accurately representing the interfaces of different material solids. The airspace above the top surface material is defined as an air solid. Boolean set operations between the various material solids and the air solid are performed to deform the wafer topography. The present invention further provides means for simulating an etch process step at the interface of materials with different etch rates.
    Type: Grant
    Filed: October 28, 1994
    Date of Patent: May 16, 1995
    Assignees: Nippon Telegraph and Telephone Corporation, Intel Corporation
    Inventors: Francisco A. Leon, Donald L. Scharfetter, Gregory Anderson, Satoshi Tazawa, Akira Yoshii
  • Patent number: 5377118
    Abstract: A method for accurately calculating the movement of a vertex in a three-dimensional (3-D) topography simulator. The method is particularly suited for calculating vertex movement for cases in which etch/deposition rate depends on the angle between the surface normal and the vertical direction. A workpiece is represented as a collection of material solids. Each of the material solids has a boundary model representation. The method of the present invention is comprised primarily of the steps of: advancing edges and surface planes adjacent to the vertex, creating a set of 2-D solutions by clipping with pairs of adjacent surface planes; creating a set of combined 2-D solutions by clipping invalid sections of combined 2-D solutions; construct an arbitrary vertical plane that intersects the surface at the vertex point; constructing vertex trajectories for the vertex to be moved; and clipping constructed vertex trajectories at intersections of created surface and the constructed vertical plane.
    Type: Grant
    Filed: June 1, 1994
    Date of Patent: December 27, 1994
    Assignee: Intel Corporation
    Inventors: Francisco A. Leon, Donald L. Scharfetter, Satoshi Tazawa, Kazuyuki Saito, Akira Yoshii