Abstract: A post-etch structure resulting in the inverse of a sidewall spacer etch, i.e. removal of the spacer. A vertical portion of a film is removed while leaving horizontal portions substantially intact. A facet is left in the film in register with an upper corner formed by the vertical and horizontal portions of the underlying body.

Abstract: Chips having subsurface structures within or adjacent a horizontal trench in bulk single crystal semiconductor are presented. Structures include three terminal devices, such as FETs and bipolar transistors, rectifying contacts, such as pn diodes and Schottky diodes, capacitors, and contacts to and connectors between devices. FETs have low resistance connectors to diffusions while retaining low overlap capacitance. A low resistance and low capacitance contact to subsurface electrodes is achieved by using highly conductive subsurface connectors which may be isolated by low dielectric insulator. Stacks of devices are formed simultaneously within bulk single crystal semiconductor. A subsurface CMOS invertor is described. A process for forming a horizontal trench exclusively in heavily doped p+ regions is presented in which porous silicon is first formed in the p+ regions and then the porous silicon is etched.

Abstract: A stacked capacitor having very thin fins and subminimum dimension supports for the fins is described. The capacitor includes a stack of conductive layers on a substrate. A plurality of subminimum dimension trenches are formed in the stack and a columnar conductive layer lines the trenches in contact with alternate layers of the stack. An insulator lines these alternate layers and the columnar conductive layer and capacitively couples these alternate layers and the columnar conductive layer to a second plate layer that is formed between the alternate layers, within the columnar layers in the trenches, and extending between stacked capacitors.

Abstract: An apparatus and method provide deposition on a surface by angled sputtering using a collimation grid having angled vanes which limit the distribution of trajectories of particles in at least one coordinate direction around a central axis oriented at an angle of less than 90.degree. to said surface; resulting in improved uniformity of deposition and/or selective favoring of deposition on surfaces at a high angle to the deposition surface (e.g. sidewalls). Substantially parallel orientation and uniform spacing of the sputtering target and deposition surface provides good uniformity of results over the deposition surface. The angled trajectories of sputtered particles provides improved deposition on sides of upstanding mandrel features and filling of recessed features of high aspect ratio, especially when the collimation grid is rotated about an axis generally perpendicular to the deposition surface.

Abstract: Chips having subsurface structures within or adjacent a horizontal trench in bulk single crystal semiconductor are presented. Structures include three terminal devices, such as FETs and bipolar transistors, rectifying contacts, such as pn diodes and Schottky diodes, capacitors, and contacts to and connectors between devices. FETs have low resistance connectors to diffusions while retaining low overlap capacitance. A low resistance and low capacitance contact to subsurface electrodes is achieved by using highly conductive subsurface connectors which may be isolated by low dielectric insulator. Stacks of devices are formed simultaneously within bulk single crystal semiconductor. A subsurface CMOS invertor is described. A process for forming a horizontal trench exclusively in heavily doped p+ regions is presented in which porous silicon is first formed in the p+ regions and then the porous silicon is etched.

Abstract: A body is provided with a substantially horizontal surface and a substantially vertical surface. A film is formed on the body with a substantially horizontal portion on the substantially horizontal surface, a substantially vertical portion on the substantially vertical surface, and a corner region joining the substantially horizontal and substantially vertical portions. The corner region and the substantially vertical portion of the film are removed while the body and the substantially horizontal portion of the film are left substantially intact. A high density plasma with a fluorocarbon-based etching gas may be used to remove the vertical portion and corner region.

Abstract: Vertical epitaxial SOI transistors and memory cells are disclosed. The devices are formed completely within a substrate trench and have a bulk channel epitaxially grown on an exposed surface of the substrate within the trench. The bulk channel is disposed proximate to a transistor gate electrode such that an inversion layer is formed therein when the gate electrode is appropriately biased. Back biasing of the bulk region is accomplished through the substrate. In the transistor embodiment, a first node diffusion and a second node diffusion are disposed at opposite ends of the bulk channel. In a memory cell configuration the access transistor is disposed above a trench storage node, which electrically connects with the transistor's second node diffusion. Arrays of the trench transistors and trench memory cells are also described. Further, fabrication methods for the various structures disclosed are presented. A novel wiring approach to construction of bit lines in a cell array is also set forth.

Abstract: The present invention is a sidewall connector providing a conductive path linking at least two conductive regions. The sidewall connector has a top portion comprising surface. A conductive member contacts the top portion, connecting the rail to a conductive region or to an external conductor. An etch stop layer located on a conductive region can be used to protect the conductive region during the directional etch to form the sidewall connector. A conductive bridge is then used to link exposed portions of the conductive region and the conductive sidewall rail, the conductive bridge extending across the thickness of the etch stop layer. A "T" connector is formed by the process, starting with a pair of intersecting sidewalls wherein the two sidewalls have top edges at different heights where they intersect. The connector is used to form a strap for a DRAM cell.

Abstract: A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion. The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes and continuous horizontally disposed program and recall gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride. The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention.

Abstract: Vertical epitaxial SOI transistors and memory cells are disclosed. The devices are formed completely within a substrate trench and have a bulk channel epitaxially grown on an exposed surface of the substrate within the trench. The bulk channel is disposed proximate to a transistor gate electrode such that an inversion layer is formed therein when the gate electrode is appropriately biased. Back biasing of the bulk region is accomplished through the substrate. In the transistor embodiment, a first node diffusion and a second node diffusion are disposed at opposite ends of the bulk channel. In a memory cell configuration the access transistor is disposed above a trench storage node, which electrically connects with the transistor's second node diffusion. Arrays of the trench transistors and trench memory cells are also described. Further, fabrication methods for the various structures disclosed are presented. A novel wiring approach to construction of bit lines in a cell array is also set forth.

Abstract: A semiconductor memory is provided wherein two bits of binary information are stored simultaneously in a ferroelectric capacitor by utilizing the positive and negative polarization states of the ferroelectric capacitor for storing a first of the two bits of binary information and by utilizing the capacitive characteristic of the ferroelectric capacitor to simultaneously store a second of the two bits of binary information without altering the polarization of the ferroelectric capacitor. When reading information from the ferroelectric capacitor, the second of the two bits of information is read out first and transferred to a buffer cell, then the first of the two bits of binary information is read and re-written, as desired, and the second of the two bits of information is returned from the buffer cell to the ferroelectric capacitor.