Abstract: A platform application specific integrated circuit (ASIC) including a base layer. The base layer generally comprises a predefined input/output (I/O) region and a predefined core region. The predefined input/output (I/O) region may comprise a plurality of pre-diffused regions disposed in the platform ASIC. The predefined core region may comprise one or more metal layers defining a plurality of power regions formed according to a custom design created after the base layer is fabricated. The base layer can be customized by depositing one or more metal layers.

Abstract: A method for interconnecting sub-functions of metal-mask programmable functions that includes the steps of (A) forming a base layer of a platform application specific integrated circuit (ASIC) comprising a plurality of pre-diffused regions disposed around a periphery of the platform ASIC, (B) forming two or more sub-functions of a function with a metal mask set placed over a number of the plurality of pre-diffused regions of the platform application specific integrated circuit and (C) configuring one or more connection points in each of the two or more sub-functions such that interconnections between the two or more sub-functions are tool routable in a single layer. Each of the pre-diffused regions is configured to be metal-programmable.

Abstract: A method for producing a chip is disclosed. A first step of the method may include fabricating the chip only up to and including a first metal layer such that a core region of the chip has an array of cells, each of the cells having a plurality of transistors. A second step generally involves designing a plurality of upper metal layers above the first metal layer in response to a custom design created after the first fabricating has started, the upper metal layers interconnecting a plurality of the cells to form (i) a mixed-signal module and (ii) a digital module, the mixed signal module generating at least one analog signal and at least one digital signal. In a third step, the method may include fabricating the chip to add the upper metal layers.

Abstract: A method for producing a chip is disclosed. A first step of the method may involve fabricating the chip only up to and including a first metal layer during a first manufacturing phase such that an input/output (I/O) region of the chip has a plurality of slots, where each of the slots has a plurality of first transistors. A second step of the method may involve designing a plurality of upper metal layers above the first metal layer in response to a custom design created after the first fabricating has started, the upper metal layers interconnecting a plurality of the first transistors to form a plurality of mixed-signal building block functions. A third step of the method may involve fabricating the chip to add the upper metal layers during a second manufacturing phase.

Abstract: A method for producing a chip is disclosed. A first step of the method may involve first fabricating the chip only up to and including a first metal layer such that a core region of the chip has an array of cells, each of the cells having a plurality of transistors. A second step of the method may be to design a plurality of upper metal layers above the first metal layer in response to a custom design created after the first fabricating has started, the upper metal layers interconnecting a plurality of the cells to form an electrostatic discharge clamp at a power domain crossing. A third step may include second fabricating the chip to add the upper metal layers.

Abstract: An apparatus including a base layer of a platform application specific integrated circuit (ASIC), a mixed-signal function and a built-in self test (BIST) function. The base layer of the platform ASIC generally includes a plurality of pre-diffused regions disposed around a periphery of the platform ASIC. Each of the pre-diffused regions is generally configured to be metal-programmable. The mixed-signal function may include two or more sub-functions formed with a metal mask set placed over a first number of the plurality of pre-diffused regions. The BIST function may be formed with a metal mask set placed over a second number of the plurality of pre-diffused regions. The BIST function may be configured to test the mixed-signal function and present a digital signal indicating an operating condition of the mixed-signal function.

Abstract: An apparatus that may include a base layer of a platform application specific integrated circuit (ASIC) and a mixed-signal function. The base layer of the platform application specific integrated circuit (ASIC) generally comprises a plurality of pre-diffused regions disposed around a periphery of the platform ASIC. Each of the pre-diffused regions may be configured to be metal-programmable. The mixed-signal function may include two or more sub-functions formed with a metal mask set placed over a number of the plurality of pre-diffused regions.

Abstract: An apparatus comprising an integrated circuit and a logic portion. The integrated circuit may have a plurality of regions each (i) pre-diffused and configured to be metal-programmed and (ii) configured to connect the integrated circuit to a socket. The logic portion may be implemented on the integrated circuit. The plurality of metal programmable regions are each (i) independently programmable and (ii) located in one of said pre-diffused regions. Each of the metal programmable regions comprises (a) a regulator section configured to generate an operating voltage from a common supply voltage, (b) a logic section configured to implement integrated circuit functions and operate at the operating voltage, and (c) a level shifter configured to shift the operating voltage to an external voltage level.

Abstract: An apparatus comprising an integrated circuit having (i) a number of regions each pre-diffused and configured to be metal-programmed and (ii) a plurality of pins configured to connect the integrated circuit to a socket. A logic portion may be implemented on the integrated circuit (i) configured to implement integrated circuit operations and (ii) having one or more I/O connections and one or more supply connections. A first group of the pre-diffused regions are metal-programmed and coupled to said I/O connections. A second group of the pre-diffused regions are metal-programmed and coupled to the supply connections.

Abstract: Circuitry and a method for testing oversampled Analog to Digital converters. The voltage reference is used as the input signal, thus eliminating the need for a special signal generator. The dynamic signal is obtained by not sampling the voltage reference on every sample. Instead, a state machine is used to gate the sampling of the voltage reference, which in turn causes a varying amount of change to be injected into the first integrator in the converter. As a result, the state machine effectively simulates many input levels.

Abstract: A multi-channel analog to digital conversion circuit and methods thereon are provided. The multi-channel analog to digital conversion cirucit comprises a plurality of linearized channels wherein each channel comprises a multi-stage pipelined charge-to-digital converter and an integrating capacitor within each stage of the multi-stage converter wherein analog residue is processed by subsequent analog to digital converter stages. Each stage of respective linearized channels is configured for calculating gain and offset for each stage in the channel and such gain and offset is used in subsequent integration periods.