Abstract: A DMT device having an analog front end for receiving an analog signal, a converter for converting the analog signal to a digital signal, a FFT for converting the digital signal from the time domain to the frequency domain and feeding the digital signal to a frequency domain equalizer having variable coefficients for flattening the converted digital signal. The frequency domain equalizer includes a gain corrector coupled to the FFT to compensate the channel frequency rolloff and make each tone approximately the same amplitude before phase rotation and a phase rotator portion responsive to the output of the gain corrector to track small channel variation. Also included is circuitry for updating the coefficients of the frequency domain equalizer, preferably in the form of a slicer for controlling the frequency domain equalizer by feeding back an error signal thereto. The error signal is preferably fed back to the phase rotator portion of the frequency domain equalizer.

Abstract: The invention provides a medium rate digital subscriber line modem solution for modem data communications between telecommunications networks and remote or end user installations over twisted metallic wire pairs.

Abstract: Methods for creating contention-free bursts of communications in an environment wherein a communications channel may be shared by a plurality of wireless networks. The methods presented also include mechanisms for recovery due to collisions and otherwise lost transmissions and for ensuring that a single wireless network is not able to obtain access of the communications channel at the expense of other wireless networks.

Abstract: Contention for a shared communications medium in a communications network involves a fine balancing act between wasting much network bandwidth sitting idle or recovering from collisions and transmitting data. Contention adaptation concepts are introduced for access to a shared medium, and adaptive algorithms for contention access using probabilities and backoffs are presented.

Abstract: The present invention provides a method, system and apparatus for managing data flow over an open system interconnection type network (10) which includes a physical layer (12) and a media access control layer (146). The invention implements a plurality of operating modules (315) each enabling a respective media access control layer operating function in which at least a portion of the operating modules are implemented in software. The invention further implements a host interface module (305) for communication between a host processor and the media access control layer, a physical layer interface module (310) for communication between the physical layer and media access control layer, and an inter-module programming interface for communications between respective operating modules.

Abstract: The present invention provides a method, system and apparatus for managing data flow over an open system interconnection type network (10) which includes a physical layer (12) and a media access control layer (146). The invention implements a plurality of operating modules (315) each enabling a respective media access control layer operating function in which at least a portion of the operating modules are implemented in software. The invention further implements a host interface module (305) for communication between a host processor and the media access control layer, a physical layer interface module (310) for communication between the physical layer and media access control layer, and an inter-module programming interface for communications between respective operating modules. The physical layer interface includes an enhanced media independent interface in accordance with some embodiments of the present invention.

Abstract: Contention communications often requires a station to wait an inordinate amount of time before the station is able to transmit its data successfully. In many applications, an extended delay is not acceptable. Contention-free communications in a contention period allows a hybrid coordinator (HC) to schedule contention-free access to a communications medium so that extended delays may be eliminated, and to coordinate contention access to the medium so that better throughput and delay performance is achieved. A method for creating contention-free communications within a contention communications period is presented, along with adaptive algorithms for contention access during the same contention period.

Abstract: A discrete multitone (DMT) digital subscriber loop (xDSL) telecommunication system has a transmitter portion including a bit encoder, inverse fast Fourier transform (FFT), parallel-to-serial converter, digital-to-analog converter and line driver for transmitting data signals to a twisted pair telephone line and a receiver portion including an analog-to-digital converter, serial-to-parallel converter, forward FFT and bit decoder for receiving data signals from the twisted pair telephone line. The FFT's are implemented in 19-bit precision using a fixed point 16-bit processor. At each FFT stage, the number of sign bits in the FFT input data is examined to determine whether overflow is possible during multiply and add operations. The input data is downscaled by right shifting one or two bits if overflow is possible. If downscaling occurred, the output data is rescaled after completion of the FFT operation. If overflow is not possible, no scaling is done.

Abstract: A modem communication system with receiving and transmission paths includes a direct equalizer system having an adaptive filter (1532) in the transmission path to compensate for frequency distortion of the communication channel. The transmitter filter coefficients are adapted by a filter coefficient calculator (1528), under control of a data detector (1526) which detects incoming data in the receiving path. A switch (1534) is controlled by status of a transmit output data buffer to multiplex either the training sequence or output data into the transmission path. When the buffer is idle, the training sequence generator (1540) is linked to a digital-to-analog (D/A) converter (1536) and line driver (1538). The receiving path includes an isolation switch (1520), a receiver amplifier (1522) and a slicer (1524). The receiver correlates the received training sequence with a known training sequence and updates the equalizer filter coefficients using an adaptation algorithm, such as a least mean squared algorithm.

Abstract: An MDSL modem is provided that is inter-operable with an ADSL modem. The present invention provides a method for modem operation, by dividing available bandwidth for the modem into a plurality of subsets, selecting at least one of the plurality of subsets for use as a communication path, reducing the SNR value used for bit loading for the selected subsets by a predetermined amount, undersampling any received data, and fast fourier transforming the received data to recover the data transmitted. An MDSL modem is provided having circuitry for dividing available bandwidth for the modem into a plurality of subsets, circuitry for selecting at least one of the plurality of subsets for use as a communication path, circuitry for reducing the SNR value used for bit loading for the selected subsets by a predetermined amount, circuitry for undersampling any received data, and circuitry for fast fourier transforming the received data to recover the data transmitted.

Abstract: A frequency-domain CAP receiver is provided that reduces the number of operations required to demodulate a CAP signal. The frequency-domain CAP receiver provides computational advantages over an equivalent time-domain version as the filter length required in the receiver increases.

Abstract: A general purpose array processor is made up of a plurality of independent processing units. A digital host computer provides the overall control for the system. An interface unit is connected to receive instructions and data signals from the host computer and then to autonomously and selectively distribute the instructions and data to other units within the system and to transmit status, control and data signals to the digital host computer. A transfer controller unit is connected to a bulk memory and to the interface unit for receiving the instructions from the interface unit and for autonomously and selectively transferring data signals from the bulk memory means to an arithmetic unit which is also connected to the interface means and receives instructions therefrom for subsequently autonomously and selectively performing arithmetic functions on the data transferred by the transfer controller unit. An input controller unit may be provided for receiving data from a data source.