Abstract: A data communication system, including at least one base station and at least one portable module 120, wherein the portable module 120 transmits data on a high frequency, and the base station transmits data on a much lower frequency. Transmissions by the base station use a pulse-width modulation scheme where the most commonly used signals correspond to the shortest pulse. A "read" command is encoded as the same pulse width as one of the two write commands. Since the direction of data transmission is known in overhead, there will be no ambiguity.

Abstract: A physical interface configuration which provides rapid contact to a two-terminal coin-shaped electronic token data module. A slot, dimensioned to receive electronic tokens, includes a grounded contact positioned to make contact to the edge of a token which may be inserted, and two data contacts which are positioned to make contact to the opposite faces of the token. Each of the data contacts is connected to an open-collector interface circuit, including a pull-up resistor which will bring the potential of the contact high when the slot is empty. The token is shaped so that its edge, and one of its faces, are connected to the token's ground line, and the other face is the token's data line. Thus, when a token is inserted (no matter which way the token is facing), one of the two data contacts will be immediately pulled to ground, by short-circuiting across the ground plane of the token.

Abstract: A latch circuit which is resistant to electrostatic discharge includes four cross-coupled NOR gate pairs located in the four corners of an integrated circuit chip, and a fifth cross-coupled NOR gate pair positioned generally in the center of the integrated circuit chip. The Q outputs, the Q outputs, the reset inputs, and the set inputs of each of the five cross-coupled NOR gate pairs are connected together such that a single cross-coupled NOR gate pair receiving an electrostatic discharge will be held in its present state by the action of the other four cross coupled NOR gate pairs which will either supply current or sink current in order to maintain the state of the Q and Q-bar outputs.

Abstract: A nonvolatile memory subsystem includes DRAMs and a battery-backed controller chip. The controller chip monitors the system power supply level to ascertain power fault conditions. When a power fault is detected, the controller provides the DRAMs with both a regulated supply voltage and appropriately timed refresh signals.After the system power supply has returned to specification, the controller continues to generate refresh control signals until the commands it to stop.

Abstract: A physical interface configuration which provides rapid contact to a two-terminal coin-shaped electronic token data module. A slot, dimensioned to receive electronic tokens, includes a grounded contact positioned to make contact to the edge of a token which may be inserted, and two data contacts which are positioned to make contact to the opposite faces of the token. Each of the data contacts is connected to an open-collector interface circuit, including a pull-up resistor which will bring the potential of the contact high when the slot is empty. The token is shaped so that its edge, and one of its faces, are connected to the token's ground line, and the other face is the token's data line. Thus, when a token is inserted (no matter which way the token is facing), one of the two data contacts will be immediately pulled to ground, by short-circuiting across the ground plane of the token.

Abstract: An electronic key which responds to different sets of valid commands over its lifetime, depending on the state of certain circuits within the electronic key.(1) After initial fabrication of the electronic key, the electronic key recognizes a first set of valid commands and ignores all other commands.(2) After the electronic key is tested and a countdown circuit within the electronic key has been calibrated, a fusing element inside the electronic key is blown. This reduces the number of valid commands recognizable by the electronic key. Thus, the key is now restricted to a second set of valid commands.(3) The electronic key is then shipped to an OEM, who programs data into the key and also programs the length of time of the countdown timer. The OEM then sets an R-S flip-flop in the electronic key, which causes certain of the second set of commands to be ignored. Thus, the key will now respond only to a third set of valid commands.(4) The electronic key is then shipped to an end user.

Abstract: A timeout circuit with internal calibration includes an oscillator (11) for generating an initial frequency for division by a modulo-n counter (20). The counter (20) receives the value of n from a calibration register (22) and divides the frequency of the oscillator by the value of n. A gate (26) prevents alteration of the contents of the register (22). The output of the counter (20) provides a calibrated frequency which is further divided by a day counter (32) for output to a countdown counter (34). The countdown counter (34) provides a predetermined countdown of the signal output by the day counter (32) and, at the end of the count, generates a Timeout signal. The predetermined countdown value is determined by a value stored in a register (36) which can be protected by a customer lock out circuit (42).

Abstract: An electronic key which responds to different sets of valid commands over its lifetime, depending on the state of certain circuits within the electronic key,(1) After initial fabrication of the electronic key, the electronic key recognizes a first set of valid commands and ignores all other commands,(2) After the electronic key is tested and a countdown circuit within the electronic key has been calibrated, a fusing element inside the electronic key is blown. This reduces the number of valid commands recognizable by the electronic key. Thus, the key is now restricted to a second set of valid commands,(3) The electronic key is then shipped to an OEM, who programs data into the key and also programs the length of time of the countdown timer. The OEM then sets an R-S flip-flop in the electronic key, which causes certain of the second set of commands to be ignored. Thus, the key will now respond only to a third set of valid commands,(4) The electronic key is then shipped to an end user.

Abstract: An oscillator with reduced temperature-dependence. A time-delay circuit uses both a pull-up resistor and a pull-down resistor, of two different types, to charge a capacitor. The material with the smallest available thermal coefficient of resistance (TCR) is used for the pull-up resistor. Another material, with a larger positive TCR, is used for the pull-down resistor. The oscillator preferably includes two separate time-delay circuits, so that the frequency of the oscillator is dependent on the charging delay of each of the time-delay circuits, but is independent of discharging delay.

Abstract: An integrated circuit random number generator which uses a triangular output analog oscillator to vary the frequency of a higher frequency voltage controlled oscillator. The output of the voltage controlled oscillator is sampled at a rate much less than the rate of oscillation of the voltage controlled oscillator to produce random digital values.

Abstract: A gated shift register includes a first set of 16 storage devices and a second set of 16 storage devices with interconnection circuitry for configuring the first set of 16 storage devices as a 16 bit shift register. The second set of storage devices is coupled between the outputs of the first set of storage devices and 16 output terminals of the gated shift register and transfers the outputs from the first storage devices to the output terminals when a transfer input terminal is at a first logic state, and isolates the first storage devices from the output terminals and retains the data at the output terminals when the transfer input signal switches to a second logic state. The gated shift register also includes power monitor and control circuitry for supplying standby battery voltage to the circuit when the primary power source becomes unavailable.

Abstract: A random number generator designed for use with an electronic key uses a triangular output analog oscillator to vary the frequency of a higher frequency voltage controlled oscillator. The output of the voltage controlled oscillator is sampled at a rate much less than the rate of oscillation of the voltage controlled oscillator to produce random digital values.

Abstract: A power controller for selectively coupling the voltage from a primary power source to a power output terminal or coupling the voltage from a battery backup input terminal to the power output terminal includes circuitry for receiving a reset or isolation signal. After receipt of the isolation signal when the primary power source is above a first threshold voltage, the primary power source and the backup battery source will be isolated from the output power terminal on the next occurrence of the removal of the voltage from the primary power source.

Abstract: A volatile/non-volatile integrated circuit memory cell combines a non-volatile cell (110) connected to a volatile cell (105) at a volatile node (118), in which data recall is effected through a DC-stable arrangement of transistor (142), (145) and (146) that does not employ a capacitor to hold down the storage node.

Abstract: A dynamic load circuit (34) selectively applies a high voltage state to a circuit node (42). A clock signal is coupled to a first node (54) and the inverse of the clock signal is coupled to a second node (60). Isolation transistors (50, 70) are controlled by the voltage level at the circuit node (42) to isolate the clock signals from the first and second nodes (54, 60) when the circuit node (42) is at a low voltage state. A high voltage signal V.sub.pp is coupled through a transistor (58) to the first node (54). The voltage at the first node (54) is coupled through a transistor (56) to the circuit node (42). The circuit node (42) is further coupled through transistors (62, 64) to the second node (60). The application of the alternating positive transistions of the clock and inverse clock signal cause the circuit (34) to apply a progressively increasing voltage to the circuit node (42).

Abstract: A nonvolatile random access memory cell (10) includes a static random access memory circuit and a corresponding nonvolatile memory circuit. The volatile memory circuit operates in a conventional manner and has first and second data states. Upon receipt of a store command signal a charge storage node is driven to either a first or a second charge state, depending upon the data state in the volatile memory circuit. For one charge state the charge storage signal is gated through a transistor (64) and a capacitor (68) to a floating gate node (44). Charge is transferred to and from the floating gate node (44) through current tunneling elements (48,50) which comprise a dielectric fabricated on a monocrystalline substrate. For the recall operation a recall command signal is applied to a transistor (52) which couples a transistor (42) to the DATA node (22) of the volatile memory circuit.