Abstract: A method and apparatus are directed to emulating an emitter follower with a small PNP transistor that is arranged in a PNP multiplier configuration. The PNP multiplier includes a PNP emitter follower and a current mirror. The PNP follower is coupled between the input and the output. A current mirror is coupled to the collector of the PNP follower such that mirror produces a current that is a scaled version of the collector current from the PNP follower. The current mirror is arranged to scale the PNP collector current by a factor of N. The effective output current from the PNP multiplier circuit corresponds to &bgr;·IIN·(N+1), where &bgr; corresponds to the large signal forward gain of the PNP follower. By multiplying the output current by a scaling factor, the effective forward gain of the PNP transistor is increased while utilizing a small geometry PNP device.

Abstract: An integrated dual-plate capacitor structure incorporates a small MOS transistor to reduce die area. The capacitor structure includes a semiconductor substrate having a first conductivity type and having a well region having a second conductivity type opposite the first conductivity type formed therein. An upper conductive plate and a lower conductive plate separated by a first layer of dielectric material are formed over the well region. The lower capacitor plate is separated from the upper surface of the well region by a second layer of dielectric material. A MOS transistor is formed in the semiconductor substrate. The MOS transistor includes space-apart source and drain regions of the second conductivity type that define a substrate channel region therebetween. A conductive gate is formed above the channel region and is separated therefrom by a layer of intervening dielectric material. The source region and the gate of the MOS transistor are connected to receive a bias voltage.