Patents by Inventor Donald W. Alderrou

Donald W. Alderrou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7457389
    Abstract: Described are a system, method and device to synchronize block data received in a data stream where the data stream is received on set data word increments. A synchronization header in each of a plurality of consecutive data word increments may be detected in a common location of a set portion or window of each consecutive fixed word increment. The data stream may be slipped by a fixed bit quantity in response to detecting an absence of the synchronization header in the common location of the set portion of a received data word increment.
    Type: Grant
    Filed: December 16, 2002
    Date of Patent: November 25, 2008
    Assignee: Intel Corporation
    Inventors: Donald W. Alderrou, Diem-Ha N. Tran
  • Patent number: 7272679
    Abstract: Transmitting data across a scalable, flexible speed, serial bus in a communication protocol independent manner.
    Type: Grant
    Filed: February 13, 2006
    Date of Patent: September 18, 2007
    Assignee: Intel Corporation
    Inventors: Richard Taborek, Sr., Donald W. Alderrou, Steve Dreyer, Gary Rara
  • Patent number: 7020729
    Abstract: Transmitting data across a scalable, flexible speed, serial bus in a communication protocol independent manner.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: March 28, 2006
    Assignee: Intel Corporation
    Inventors: Richard Taborek, Sr., Donald W. Alderrou, Steve Dreyer, Gary Rara
  • Publication number: 20040114699
    Abstract: Described are a system, method and device to synchronize block data received in a data stream where the data stream is received on set data word increments. A synchronization header in each of a plurality of consecutive data word increments may be detected in a common location of a set portion or window of each consecutive fixed word increment. The data stream may be slipped by a fixed bit quantity in response to detecting an absence of the synchronization header in the common location of the set portion of a received data word increment.
    Type: Application
    Filed: December 16, 2002
    Publication date: June 17, 2004
    Inventors: Donald W. Alderrou, Diem-Ha N. Tran
  • Patent number: 6724725
    Abstract: A method operates a media access control device. The method includes (a) detecting the assertion of a flow control condition, (b) generating a PAUSE frame in response to the detection of a flow control condition, the PAUSE frame directing a remote device to PAUSE for a first amount of time, (c) causing the media access device to wait for a second amount of time, the second amount of time being less than or equal to the first amount of time, and (d) generating, upon expiration of the second amount of time and the continued assertion of the flow control condition, an additional PAUSE frame directing a remote device to PAUSE for a first amount of time.
    Type: Grant
    Filed: April 11, 2000
    Date of Patent: April 20, 2004
    Assignee: LSI Logic Corporation
    Inventors: Stephen F. Dreyer, Eric T. West, Donald W. Alderrou
  • Publication number: 20030235203
    Abstract: Disclosed is an extender sublayer device comprising an MII to transmit data between the MII and a plurality of data lanes in an AUI. The extender sublayer device comprises a plurality of internal device pins and a plurality of external device pins where at least some of the external device pins are associated with data lanes in the AUI. Logic may selectively couple the one or more internal circuit pins to one of the external device pins in response to an external control signal.
    Type: Application
    Filed: June 25, 2002
    Publication date: December 25, 2003
    Inventors: Donald W. Alderrou, Frederick Buckley
  • Publication number: 20030217215
    Abstract: Transmitting data across a scalable, flexible speed, serial bus in a communication protocol independent manner.
    Type: Application
    Filed: May 16, 2002
    Publication date: November 20, 2003
    Inventors: Richard Taborek, Donald W. Alderrou, Steve Dreyer, Gary Rara
  • Patent number: 6098103
    Abstract: Pre-formatted MAC Control PAUSE frames are generated by a MAC device rather than by a switch. These may be automatically generated and transmitted upon the occurrence of a full or near full condition in the input buffer of the MAC device. The MAC device, upon receipt of a MAC Control PAUSE frame, allows a packet in the process of being transmitted to complete transmission prior to implementing the PAUSE. The MAC device is capable of generating MAC Control frames having any desired opcode. The parameter field associated with the MAC Control frame opcode is programmable. The destination address of the MAC Control frame is programmable. Automatic x-on/x-off is implemented. Flags may be set to enable/disable the IEEE 802.3x pause function in the MAC device and to override basic IEEE 802.3x operation in various ways.
    Type: Grant
    Filed: August 11, 1997
    Date of Patent: August 1, 2000
    Assignee: LSI Logic Corporation
    Inventors: Stephen F. Dreyer, Eric T. West, Donald W. Alderrou