Abstract: A bus interface is partitionable into at least two slices. Each slice interfaces a respective subset of data from a computer device to a system bus. Each slice also receives a corresponding subset of control information and a complete set of address information from the computer device. Moreover, each slice may be implemented on a single integrated circuit chip, which thus handles both data and control functions.

Abstract: A bus interface is partitionable into at least two slices. Each slice interfaces a respective subset of data from a computer device to a system bus. Each slice also receives a corresponding subset of control information and a complete set of address information from the computer device. Moreover, each slice may be implemented on a single integrated circuit chip, which thus handles both data and control functions.

Abstract: A memory system has a stream buffer with several performance-enhancing features. Two distinct sets of latches receive data from the memory array. One set feeds the stream buffer, while the other holds memory data that is destined for a system bus. The dual-latch configuration allows stream buffer fills to proceed even if system bus stalls prevent the memory data latch from being timely emptied. The memory controller prefetches a number of data blocks depending on the interleave factor of the memory system, as well as in response to control information from the CPU that can override the interleave-based number in some system configurations. The stream buffer employs a history buffer containing the addresses of recently-read memory locations in order to declare a new stream. The addresses of memory reads are normally entered into the history buffer on a round-robin basis.

Abstract: A system and method that reduces the simultaneous switching noise of outputs and the processing delays caused by inductance by using an encoding scheme that results in a net signaling current of substantially zero at each cycle time for the fast parallel switching networks of digital integrated circuit chips and that provides multiple types of error detection.

Abstract: The operation of a stream buffer varies depending on whether a normal operation mode or a test mode is selected. In the normal operation mode, the stream buffer is read from only when the data requested by a CPU read has been determined to reside there, and the stream buffer location read from is the location determined to contain the requested data. This determination is made by comparing the address of the read request with addresses of the data stored in the stream buffer. Also, the stream buffer is written with memory data in response to a read that misses the stream buffer, and the location written to is one that has been allocated to receive the incoming memory data. Two different buffer allocation methods are shown, first-in-first-out (FIFO) and least-recently-used (LRU).

Abstract: A fault tolerant addressing arrangement for a solid-state disk comprising partially defective memory devices is provided. The addressing technique increments both row and column addresses when establishing locations for the storage of symbols so that the same rows and columns are not addressed for any two symbols. The technique also complements certain portions of the symbols' address to ensure addressing of different locations within each memory device.

Abstract: System for testing memory associated with a set of check bits in an EDC system. The circuitry of the invention includes an EDC circuit; multiplexers; and a memory with first storage bits, second storage bits, and third storage bits. In writing data to the memory, a multi-bit data word having a first group of data bits and a second group of data bits is first received from a CPU bus. The first group of bits is written to the first storage bits. In a "normal" mode, the second group of bits is written to the second storage bits. A set of check bits are calculated by the EDC circuit and written to the third storage bits. In the "swap" mode, the second group of data bits is stored in the third storage bits. "Alternate" bits are calculated by the EDC circuit, and written to the second storage bits. In memory reads, contents of all of the storage bits are received from the memory and directed to the error detecting circuit. The contents of the first storage bits are directed to error correction circuit.

Abstract: A method and apparatus for implementing a capture of a long contiguous chain of data bus cycles for the memory system of a data processing system with memory units that alternate between real time capture of segments of the chain of data bus cycles and processing of the data bus signals in the captured segments.

Abstract: A memory testing system for an electronic computing system includes multiple memory modules, each equipped with error detecting and correcting (EDC) circuitry, and is operable in a diagnostic test mode wherein read and write tests of the modules are performed in parallel. Each module includes a command/status register (CSR), used in identifying errors occurring in that module by capturing various signals at the time of the error. These signals include the type of error, the memory address involved in the error, the check bits of the data associated with the error, and the syndromes of the data. After pre-setting each CSR's diagnostic register, one module operates in a "target" mode, and the remaining modules operate in a "shadow" mode. The target module operates normally during read and write operations. When the target module is directed to write data to a particular address, the shadow modules write the same data to corresponding addresses in their memory banks.

Abstract: A low-profile, high-density package for intergrated circuit chips is provided. A first multichip memory module includes first and second interconnect members having low-profile memory chips mounted on a first side of each member. Low-profile edge clips are employed to mechanically connect a second side of the second member to a second side of the first member, and to electrically connect the first sides of the members to a first surface of a circuit board. Likewise, a second multichip memory module includes first and second interconnect members having low-profile memory chips mounted to a first side of each member. Low-profile edge clips are employed to mechanically connect the second sides of the members, and to electrically connect the first sides of the members to a second surface of the circuit board. A thermal management technique that distributes thermal loads is thereafter applied to create a high-density package capable of insertion into a standard computer backplane and cabinet.

Abstract: An error detection and correction scheme is provided utilizing a modified Reed-Solomon code which has been optimized to detect erroneous memory location accessing and catastrophic failure condition of data containing either all ones or all zeros for N-bit wide semiconductor random access memories. When data is written to memory, the scheme calculates a series of check bits to represent a data word and the address of the location that the data word is to be stored and stores that information in memory. When data is read from memory, a series of syndromes are calculated based upon the data read and its memory location. These syndromes are compared which enables the system to detect which symbol of the data word an error occurs and the corrected value of that symbol.

Abstract: A method and apparatus for testing each memory location of a memory device, the method comprising the steps of: generating each of the memory addresses corresponding to each memory location in a pseudo-random order; generating a pseudo-random series of data words; storing one of the data words at each memory location; reading each data word back from memory; regenerating the series of data words; and comparing each read data word to the corresponding regenerated data word. The invention features generating and storing a second series of data words, each data word being inverse of the data words in the first series. The second series of data words are read from memory and compared to regenerated data. The invention also features a novel linear feedback shift register for generating the pseudo-random memory addresses and can generate the address zero. An accumulating register is utilized to store the approximate location of malfunctioning memory locations.

Abstract: An algorithm, and methodology for its application, useful in digital computer systems incorporating read-modify-write data storage systems to accurately identify rewritten data which has been determined bad before being rewritten.

Abstract: A DRAM test system includes a storage location tester and controller tester. The storage location tester utilizes an error correction code which generates redundancy symbols corresponding to inverted data that are the binary inverse or compliment of the redundancy symbols corresponding to the non-inverted data. Thus each bit-location of an addressable storage location, consisting of both data and ECC redundancy bit locations, can be fully tested for storage and retrieval of both a ONE and a ZERO in only three read/write cycles. The controller tester tests the DRAM controller circuitry by sequencing it through various operations, at least one of which is a refresh operation. When a refresh operation occurs the node signals corresponding to the refresh operation are incorporated into a DRAM controller signature vector.

Abstract: A method and apparatus for error detection is disclosed. A data word and its check bits are read from memory, and new check bits are generated form the data word read. A logical operation is performed between the new check bits and the check bits read from memory to generate a syndrome. The syndrome is decoded to detect the presence or absence of an uncorrectable error. If an uncorrectable error is detected, a logical operation is performed between the new check bits and a byte write error code to generate a third set of check bits, which are then written into memory along with the data word.

Abstract: A method and apparatus for memory testing is described. A first pattern of data is written into the memory in a pseudo-random address sequence determined by an address generator. The first pattern is read from the memory and checked for any error. A second pattern that is the complement of the first pattern is written into the memory in a pseudo-random address sequence determined by the address generator. The second pattern is read from the memory and checked for any errors. A third pattern of data is written into the memory in the pseudo-random address sequence determined by the address generator. The third pattern of data has the effect of complementing respective check bits which are the same for the first pattern of data and the second pattern of data. The third pattern is read from memory and checked for any error.